stm32f10x_usart.txt

STM32外部SRAM用作datamemery的程序 开发环境MDK

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_usart.o --depend=.\Obj\stm32f10x_usart.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_usart.crf ..\..\..\FWLib\library\src\stm32f10x_usart.c]
                          THUMB

                          AREA ||i.USART_DeInit||, CODE, READONLY, ALIGN=2

                  USART_DeInit PROC
;;;94     
;;;95       switch (*(u32*)&USARTx)
000000  4a18              LDR      r2,|L1.100|
000002  b510              PUSH     {r4,lr}
000004  1a81              SUBS     r1,r0,r2
000006  1513              ASRS     r3,r2,#20
000008  4290              CMP      r0,r2
00000a  d01b              BEQ      |L1.68|
00000c  dc07              BGT      |L1.30|
00000e  4916              LDR      r1,|L1.104|
000010  1840              ADDS     r0,r0,r1
000012  d014              BEQ      |L1.62|
000014  4298              CMP      r0,r3
000016  d123              BNE      |L1.96|
;;;96       {
;;;97         case USART1_BASE:
;;;98           RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
;;;99           RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
;;;100          break;
;;;101    
;;;102        case USART2_BASE:
;;;103          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
;;;104          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
;;;105          break;
;;;106    
;;;107        case USART3_BASE:
;;;108          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
000018  2101              MOVS     r1,#1
00001a  048c              LSLS     r4,r1,#18
;;;109          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
;;;110          break;
00001c  e017              B        |L1.78|
                  |L1.30|
00001e  4299              CMP      r1,r3                 ;95
000020  d013              BEQ      |L1.74|
000022  f5b1f5b1          CMP      r1,#0xec00            ;95
000026  d11b              BNE      |L1.96|
000028  2101              MOVS     r1,#1                 ;98
00002a  038c              LSLS     r4,r1,#14             ;98
00002c  4620              MOV      r0,r4                 ;98
00002e  f7fff7ff          BL       RCC_APB2PeriphResetCmd
000032  4620              MOV      r0,r4                 ;99
000034  e8bde8bd          POP      {r4,lr}               ;99
000038  2100              MOVS     r1,#0                 ;99
00003a  f7fff7ff          B.W      RCC_APB2PeriphResetCmd
                  |L1.62|
00003e  2101              MOVS     r1,#1                 ;103
000040  044c              LSLS     r4,r1,#17             ;103
000042  e004              B        |L1.78|
                  |L1.68|
;;;111        
;;;112        case UART4_BASE:
;;;113          RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
000044  2101              MOVS     r1,#1
000046  04cc              LSLS     r4,r1,#19
;;;114          RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
;;;115          break;
000048  e001              B        |L1.78|
                  |L1.74|
;;;116        
;;;117        case UART5_BASE:
;;;118          RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
00004a  2101              MOVS     r1,#1
00004c  050c              LSLS     r4,r1,#20
                  |L1.78|
00004e  4620              MOV      r0,r4
000050  f7fff7ff          BL       RCC_APB1PeriphResetCmd
;;;119          RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
000054  4620              MOV      r0,r4
000056  e8bde8bd          POP      {r4,lr}
00005a  2100              MOVS     r1,#0
00005c  f7fff7ff          B.W      RCC_APB1PeriphResetCmd
                  |L1.96|
;;;120          break;            
;;;121    
;;;122        default:
;;;123          break;
;;;124      }
;;;125    }
000060  bd10              POP      {r4,pc}
;;;126    
                          ENDP

000062  0000              DCW      0x0000
                  |L1.100|
000064  40004c00          DCD      0x40004c00
                  |L1.104|
000068  bfffbc00          DCD      0xbfffbc00

                          AREA ||i.USART_Init||, CODE, READONLY, ALIGN=2

                  USART_Init PROC
;;;140    void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
;;;141    {
000000  b530              PUSH     {r4,r5,lr}
000002  4604              MOV      r4,r0
;;;142      u32 tmpreg = 0x00, apbclock = 0x00;
;;;143      u32 integerdivider = 0x00;
;;;144      u32 fractionaldivider = 0x00;
;;;145      u32 usartxbase = 0;
;;;146      RCC_ClocksTypeDef RCC_ClocksStatus;
;;;147    
;;;148      /* Check the parameters */
;;;149      assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;150      assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
;;;151      assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
;;;152      assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
;;;153      assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
;;;154      assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
;;;155      assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
;;;156      /* The hardware flow control is available only for USART1, USART2 and USART3 */          
;;;157      assert_param(IS_USART_PERIPH_HFC(USARTx, USART_InitStruct->USART_HardwareFlowControl));
;;;158      
;;;159      usartxbase = (*(u32*)&USARTx);
;;;160    
;;;161    /*---------------------------- USART CR2 Configuration -----------------------*/
;;;162      tmpreg = USARTx->CR2;
000004  8a00              LDRH     r0,[r0,#0x10]
000006  b085              SUB      sp,sp,#0x14           ;141
000008  460d              MOV      r5,r1                 ;141
;;;163      /* Clear STOP[13:12] bits */
;;;164      tmpreg &= CR2_STOP_CLEAR_Mask;
00000a  f64cf64c          MOV      r1,#0xcfff
00000e  4008              ANDS     r0,r0,r1
;;;165    
;;;166      /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
;;;167      /* Set STOP[13:12] bits according to USART_StopBits value */
;;;168      tmpreg |= (u32)USART_InitStruct->USART_StopBits;
000010  88e9              LDRH     r1,[r5,#6]
000012  4301              ORRS     r1,r1,r0
;;;169      
;;;170      /* Write to USART CR2 */
;;;171      USARTx->CR2 = (u16)tmpreg;
000014  8221              STRH     r1,[r4,#0x10]
;;;172    
;;;173    /*---------------------------- USART CR1 Configuration -----------------------*/
;;;174      tmpreg = USARTx->CR1;
000016  89a0              LDRH     r0,[r4,#0xc]
;;;175      /* Clear M, PCE, PS, TE and RE bits */
;;;176      tmpreg &= CR1_CLEAR_Mask;
000018  f64ef64e          MOV      r1,#0xe9f3
00001c  4008              ANDS     r0,r0,r1
;;;177    
;;;178      /* Configure the USART Word Length, Parity and mode ----------------------- */
;;;179      /* Set the M bits according to USART_WordLength value */
;;;180      /* Set PCE and PS bits according to USART_Parity value */
;;;181      /* Set TE and RE bits according to USART_Mode value */
;;;182      tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
00001e  88a9              LDRH     r1,[r5,#4]
000020  892a              LDRH     r2,[r5,#8]
000022  4311              ORRS     r1,r1,r2
000024  896a              LDRH     r2,[r5,#0xa]
000026  4302              ORRS     r2,r2,r0
000028  4311              ORRS     r1,r1,r2
;;;183                USART_InitStruct->USART_Mode;
;;;184    
;;;185      /* Write to USART CR1 */
;;;186      USARTx->CR1 = (u16)tmpreg;
00002a  81a1              STRH     r1,[r4,#0xc]
;;;187    
;;;188    /*---------------------------- USART CR3 Configuration -----------------------*/  
;;;189      tmpreg = USARTx->CR3;
00002c  8aa0              LDRH     r0,[r4,#0x14]
;;;190      /* Clear CTSE and RTSE bits */
;;;191      tmpreg &= CR3_CLEAR_Mask;
00002e  f64ff64f          MOV      r1,#0xfcff
000032  4008              ANDS     r0,r0,r1
;;;192    
;;;193      /* Configure the USART HFC -------------------------------------------------*/
;;;194      /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
;;;195      tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
000034  89a9              LDRH     r1,[r5,#0xc]
000036  4301              ORRS     r1,r1,r0
;;;196    
;;;197      /* Write to USART CR3 */
;;;198      USARTx->CR3 = (u16)tmpreg;
000038  82a1              STRH     r1,[r4,#0x14]
;;;199    
;;;200    /*---------------------------- USART BRR Configuration -----------------------*/
;;;201      /* Configure the USART Baud Rate -------------------------------------------*/
;;;202      RCC_GetClocksFreq(&RCC_ClocksStatus);
00003a  4668              MOV      r0,sp
00003c  f7fff7ff          BL       RCC_GetClocksFreq
;;;203      if (usartxbase == USART1_BASE)
000040  4810              LDR      r0,|L2.132|
000042  4284              CMP      r4,r0
000044  d101              BNE      |L2.74|
;;;204      {
;;;205        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
000046  9803              LDR      r0,[sp,#0xc]
000048  e000              B        |L2.76|
                  |L2.74|
;;;206      }
;;;207      else
;;;208      {
;;;209        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
00004a  9802              LDR      r0,[sp,#8]
                  |L2.76|
;;;210      }
;;;211    
;;;212      /* Determine the integer part */
;;;213      integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
00004c  2119              MOVS     r1,#0x19
00004e  4348              MULS     r0,r1,r0
000050  6829              LDR      r1,[r5,#0]
;;;214      tmpreg = (integerdivider / 0x64) << 0x04;
000052  2264              MOVS     r2,#0x64
000054  0089              LSLS     r1,r1,#2              ;213
000056  fbb0fbb0          UDIV     r0,r0,r1              ;213
00005a  fbb0fbb0          UDIV     r1,r0,r2
00005e  0109              LSLS     r1,r1,#4
;;;215    
;;;216      /* Determine the fractional part */
;;;217      fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
000060  090b              LSRS     r3,r1,#4
000062  f06ff06f          MVN      r5,#0x18
000066  436b              MULS     r3,r5,r3
;;;218      tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
000068  2532              MOVS     r5,#0x32
00006a  eb00eb00          ADD      r0,r0,r3,LSL #2       ;217
00006e  eb05eb05          ADD      r0,r5,r0,LSL #4
000072  fbb0fbb0          UDIV     r0,r0,r2
000076  f000f000          AND      r0,r0,#0xf
00007a  4308              ORRS     r0,r0,r1
;;;219    
;;;220      /* Write to USART BRR */
;;;221      USARTx->BRR = (u16)tmpreg;
00007c  8120              STRH     r0,[r4,#8]
;;;222    }
00007e  b005              ADD      sp,sp,#0x14
000080  bd30              POP      {r4,r5,pc}
;;;223    
                          ENDP

000082  0000              DCW      0x0000
                  |L2.132|
000084  40013800          DCD      0x40013800

                          AREA ||i.USART_StructInit||, CODE, READONLY, ALIGN=1

                  USART_StructInit PROC
;;;234      /* USART_InitStruct members default value */
;;;235      USART_InitStruct->USART_BaudRate = 9600;
000000  f44ff44f          MOV      r1,#0x2580
;;;236      USART_InitStruct->USART_WordLength = USART_WordLength_8b;
000004  6001              STR      r1,[r0,#0]
000006  2100              MOVS     r1,#0
000008  8081              STRH     r1,[r0,#4]
;;;237      USART_InitStruct->USART_StopBits = USART_StopBits_1;
00000a  80c1              STRH     r1,[r0,#6]
;;;238      USART_InitStruct->USART_Parity = USART_Parity_No ;
00000c  8101              STRH     r1,[r0,#8]
;;;239      USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00000e  220c              MOVS     r2,#0xc
000010  8142              STRH     r2,[r0,#0xa]
;;;240      USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
000012  8181              STRH     r1,[r0,#0xc]
;;;241    }
000014  4770              BX       lr
;;;242    
                          ENDP


                          AREA ||i.USART_ClockInit||, CODE, READONLY, ALIGN=1

                  USART_ClockInit PROC
;;;255    void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
;;;256    {
000000  b530              PUSH     {r4,r5,lr}
;;;257      u32 tmpreg = 0x00;
;;;258    
;;;259      /* Check the parameters */
;;;260      assert_param(IS_USART_123_PERIPH(USARTx));
;;;261      assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
;;;262      assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
;;;263      assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
;;;264      assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));              
;;;265      
;;;266    /*---------------------------- USART CR2 Configuration -----------------------*/
;;;267      tmpreg = USARTx->CR2;
000002  8a02              LDRH     r2,[r0,#0x10]
;;;268      /* Clear CLKEN, CPOL, CPHA and LBCL bits */
;;;269      tmpreg &= CR2_CLOCK_CLEAR_Mask;
000004  f24ff24f          MOV      r3,#0xf0ff
000008  401a              ANDS     r2,r2,r3
;;;270    
;;;271      /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
;;;272      /* Set CLKEN bit according to USART_Clock value */
;;;273      /* Set CPOL bit according to USART_CPOL value */
;;;274      /* Set CPHA bit according to USART_CPHA value */
;;;275      /* Set LBCL bit according to USART_LastBit value */
;;;276      tmpreg |= (u32)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
00000a  880b              LDRH     r3,[r1,#0]
00000c  884d              LDRH     r5,[r1,#2]
00000e  888c              LDRH     r4,[r1,#4]
000010  88c9              LDRH     r1,[r1,#6]
000012  432b              ORRS     r3,r3,r5
000014  430c              ORRS     r4,r4,r1
000016  4323              ORRS     r3,r3,r4
000018  4313              ORRS     r3,r3,r2
;;;277                     USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
;;;278    
;;;279      /* Write to USART CR2 */
;;;280      USARTx->CR2 = (u16)tmpreg;
00001a  8203              STRH     r3,[r0,#0x10]
;;;281    }
00001c  bd30              POP      {r4,r5,pc}
;;;282    
                          ENDP