stm32f10x_fsmc.txt

STM32外部SRAM用作datamemery的程序 开发环境MDK

;;;637      assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;638      assert_param(IS_FSMC_IT(FSMC_IT));	
;;;639      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;640      
;;;641      if (NewState != DISABLE)
00000a  b16a              CBZ      r2,|L15.40|
;;;642      {
;;;643        /* Enable the selected FSMC_Bank2 interrupts */
;;;644        if(FSMC_Bank == FSMC_Bank2_NAND)
00000c  2810              CMP      r0,#0x10
00000e  d102              BNE      |L15.22|
;;;645        {
;;;646          FSMC_Bank2->SR2 |= FSMC_IT;
000010  6e58              LDR      r0,[r3,#0x64]
000012  4308              ORRS     r0,r0,r1
000014  e00c              B        |L15.48|
                  |L15.22|
;;;647        }
;;;648        /* Enable the selected FSMC_Bank3 interrupts */
;;;649        else if (FSMC_Bank == FSMC_Bank3_NAND)
000016  42a0              CMP      r0,r4
000018  d101              BNE      |L15.30|
00001a  3384              ADDS     r3,r3,#0x84
;;;650        {
;;;651          FSMC_Bank3->SR3 |= FSMC_IT;
00001c  e000              B        |L15.32|
                  |L15.30|
00001e  33a4              ADDS     r3,r3,#0xa4
                  |L15.32|
;;;652        }
;;;653        /* Enable the selected FSMC_Bank4 interrupts */
;;;654        else
;;;655        {
;;;656          FSMC_Bank4->SR4 |= FSMC_IT;    
000020  6818              LDR      r0,[r3,#0]
000022  4308              ORRS     r0,r0,r1
                  |L15.36|
000024  6018              STR      r0,[r3,#0]
;;;657        }
;;;658      }
;;;659      else
;;;660      {
;;;661        /* Disable the selected FSMC_Bank2 interrupts */
;;;662        if(FSMC_Bank == FSMC_Bank2_NAND)
;;;663        {
;;;664          
;;;665          FSMC_Bank2->SR2 &= (u32)~FSMC_IT;
;;;666        }
;;;667        /* Disable the selected FSMC_Bank3 interrupts */
;;;668        else if (FSMC_Bank == FSMC_Bank3_NAND)
;;;669        {
;;;670          FSMC_Bank3->SR3 &= (u32)~FSMC_IT;
;;;671        }
;;;672        /* Disable the selected FSMC_Bank4 interrupts */
;;;673        else
;;;674        {
;;;675          FSMC_Bank4->SR4 &= (u32)~FSMC_IT;    
;;;676        }
;;;677      }
;;;678    }
000026  bd10              POP      {r4,pc}
                  |L15.40|
000028  2810              CMP      r0,#0x10              ;662
00002a  d103              BNE      |L15.52|
00002c  6e58              LDR      r0,[r3,#0x64]         ;665
00002e  4388              BICS     r0,r0,r1              ;665
                  |L15.48|
000030  6658              STR      r0,[r3,#0x64]         ;646
000032  bd10              POP      {r4,pc}
                  |L15.52|
000034  42a0              CMP      r0,r4                 ;668
000036  d101              BNE      |L15.60|
000038  3384              ADDS     r3,r3,#0x84           ;668
00003a  e000              B        |L15.62|
                  |L15.60|
00003c  33a4              ADDS     r3,r3,#0xa4           ;670
                  |L15.62|
00003e  6818              LDR      r0,[r3,#0]            ;670
000040  4388              BICS     r0,r0,r1              ;670
000042  e7ef              B        |L15.36|
;;;679                      
                          ENDP


                          AREA ||i.FSMC_GetFlagStatus||, CODE, READONLY, ALIGN=1

                  FSMC_GetFlagStatus PROC
;;;697    FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG)
;;;698    {
000000  4603              MOV      r3,r0
;;;699      FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
000004  f04ff04f          MOV      r2,#0xa0000000
;;;700      u32 tmpsr = 0x00000000;
;;;701      
;;;702      /* Check the parameters */
;;;703      assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
;;;704      assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
;;;705      
;;;706      if(FSMC_Bank == FSMC_Bank2_NAND)
000008  2b10              CMP      r3,#0x10
00000a  d101              BNE      |L16.16|
;;;707      {
;;;708        tmpsr = FSMC_Bank2->SR2;
00000c  6e52              LDR      r2,[r2,#0x64]
00000e  e007              B        |L16.32|
                  |L16.16|
;;;709      }  
;;;710      else if(FSMC_Bank == FSMC_Bank3_NAND)
000010  f5b3f5b3          CMP      r3,#0x100
000014  d102              BNE      |L16.28|
;;;711      {
;;;712        tmpsr = FSMC_Bank3->SR3;
000016  f8d2f8d2          LDR      r2,[r2,#0x84]
00001a  e001              B        |L16.32|
                  |L16.28|
;;;713      }
;;;714      /* FSMC_Bank4_PCCARD*/
;;;715      else
;;;716      {
;;;717        tmpsr = FSMC_Bank4->SR4;
00001c  f8d2f8d2          LDR      r2,[r2,#0xa4]
                  |L16.32|
;;;718      } 
;;;719      
;;;720      /* Get the flag status */
;;;721      if ((tmpsr & FSMC_FLAG) != (u16)RESET )
000020  420a              TST      r2,r1
000022  d000              BEQ      |L16.38|
;;;722      {
;;;723        bitstatus = SET;
000024  2001              MOVS     r0,#1
                  |L16.38|
;;;724      }
;;;725      else
;;;726      {
;;;727        bitstatus = RESET;
;;;728      }
;;;729      /* Return the flag status */
;;;730      return bitstatus;
;;;731    }
000026  4770              BX       lr
;;;732    
                          ENDP


                          AREA ||i.FSMC_ClearFlag||, CODE, READONLY, ALIGN=1

                  FSMC_ClearFlag PROC
;;;749    void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG)
;;;750    {
000000  f04ff04f          MOV      r2,#0xa0000000
;;;751     /* Check the parameters */
;;;752      assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
;;;753      assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
;;;754        
;;;755      if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2810              CMP      r0,#0x10
000006  d103              BNE      |L17.16|
;;;756      {
;;;757        FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
000008  6e50              LDR      r0,[r2,#0x64]
00000a  4388              BICS     r0,r0,r1
00000c  6650              STR      r0,[r2,#0x64]
;;;758      }  
;;;759      else if(FSMC_Bank == FSMC_Bank3_NAND)
;;;760      {
;;;761        FSMC_Bank3->SR3 &= ~FSMC_FLAG;
;;;762      }
;;;763      /* FSMC_Bank4_PCCARD*/
;;;764      else
;;;765      {
;;;766        FSMC_Bank4->SR4 &= ~FSMC_FLAG;
;;;767      }
;;;768    }
00000e  4770              BX       lr
                  |L17.16|
000010  f5b0f5b0          CMP      r0,#0x100             ;759
000014  d101              BNE      |L17.26|
000016  3284              ADDS     r2,r2,#0x84           ;759
000018  e000              B        |L17.28|
                  |L17.26|
00001a  32a4              ADDS     r2,r2,#0xa4           ;761
                  |L17.28|
00001c  6810              LDR      r0,[r2,#0]            ;766
00001e  4388              BICS     r0,r0,r1              ;766
000020  6010              STR      r0,[r2,#0]            ;766
000022  4770              BX       lr
;;;769    
                          ENDP


                          AREA ||i.FSMC_GetITStatus||, CODE, READONLY, ALIGN=1

                  FSMC_GetITStatus PROC
;;;786    ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT)
;;;787    {
000000  4603              MOV      r3,r0
;;;788      ITStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
000004  f04ff04f          MOV      r2,#0xa0000000
;;;789      u32 tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
;;;790      
;;;791      /* Check the parameters */
;;;792      assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;793      assert_param(IS_FSMC_GET_IT(FSMC_IT));
;;;794      
;;;795      if(FSMC_Bank == FSMC_Bank2_NAND)
000008  2b10              CMP      r3,#0x10
00000a  d101              BNE      |L18.16|
;;;796      {
;;;797        tmpsr = FSMC_Bank2->SR2;
00000c  6e52              LDR      r2,[r2,#0x64]
00000e  e007              B        |L18.32|
                  |L18.16|
;;;798      }  
;;;799      else if(FSMC_Bank == FSMC_Bank3_NAND)
000010  f5b3f5b3          CMP      r3,#0x100
000014  d102              BNE      |L18.28|
;;;800      {
;;;801        tmpsr = FSMC_Bank3->SR3;
000016  f8d2f8d2          LDR      r2,[r2,#0x84]
00001a  e001              B        |L18.32|
                  |L18.28|
;;;802      }
;;;803      /* FSMC_Bank4_PCCARD*/
;;;804      else
;;;805      {
;;;806        tmpsr = FSMC_Bank4->SR4;
00001c  f8d2f8d2          LDR      r2,[r2,#0xa4]
                  |L18.32|
;;;807      } 
;;;808      
;;;809      itstatus = tmpsr & FSMC_IT;
000020  420a              TST      r2,r1
;;;810      
;;;811      itenable = tmpsr & (FSMC_IT >> 3);
000022  ea02ea02          AND      r1,r2,r1,LSR #3
;;;812    
;;;813      if ((itstatus != (u32)RESET)  && (itenable != (u32)RESET))
000026  d002              BEQ      |L18.46|
000028  2900              CMP      r1,#0
00002a  d000              BEQ      |L18.46|
;;;814      {
;;;815        bitstatus = SET;
00002c  2001              MOVS     r0,#1
                  |L18.46|
;;;816      }
;;;817      else
;;;818      {
;;;819        bitstatus = RESET;
;;;820      }
;;;821      return bitstatus; 
;;;822    }
00002e  4770              BX       lr
;;;823    
                          ENDP


                          AREA ||i.FSMC_ClearITPendingBit||, CODE, READONLY, ALIGN=1

                  FSMC_ClearITPendingBit PROC
;;;840    void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT)
;;;841    {
000000  f04ff04f          MOV      r2,#0xa0000000
;;;842      /* Check the parameters */
;;;843      assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;844      assert_param(IS_FSMC_IT(FSMC_IT));
;;;845        
;;;846      if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2810              CMP      r0,#0x10
000006  d104              BNE      |L19.18|
;;;847      {
;;;848        FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
000008  6e50              LDR      r0,[r2,#0x64]
00000a  ea20ea20          BIC      r0,r0,r1,LSR #3
00000e  6650              STR      r0,[r2,#0x64]
;;;849      }  
;;;850      else if(FSMC_Bank == FSMC_Bank3_NAND)
;;;851      {
;;;852        FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
;;;853      }
;;;854      /* FSMC_Bank4_PCCARD*/
;;;855      else
;;;856      {
;;;857        FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
;;;858      }
;;;859    }
000010  4770              BX       lr
                  |L19.18|
000012  f5b0f5b0          CMP      r0,#0x100             ;850
000016  d101              BNE      |L19.28|
000018  3284              ADDS     r2,r2,#0x84           ;850
00001a  e000              B        |L19.30|
                  |L19.28|
00001c  32a4              ADDS     r2,r2,#0xa4           ;852
                  |L19.30|
00001e  6810              LDR      r0,[r2,#0]            ;857
000020  ea20ea20          BIC      r0,r0,r1,LSR #3       ;857
000024  6010              STR      r0,[r2,#0]            ;857
000026  4770              BX       lr
;;;860    
                          ENDP