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📄 stm32f10x_fsmc.txt

📁 STM32外部SRAM用作datamemery的程序 开发环境MDK
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000036  4770              BX       lr
;;;417    
                          ENDP


                          AREA ||i.FSMC_PCCARDStructInit||, CODE, READONLY, ALIGN=1

                  FSMC_PCCARDStructInit PROC
;;;428      /* Reset PCCARD Init structure parameters values */
;;;429      FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000000  2100              MOVS     r1,#0
;;;430      FSMC_PCCARDInitStruct->FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
000002  6001              STR      r1,[r0,#0]
;;;431      FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
000004  6041              STR      r1,[r0,#4]
;;;432      FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
000006  6081              STR      r1,[r0,#8]
;;;433      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000008  60c1              STR      r1,[r0,#0xc]
00000a  6902              LDR      r2,[r0,#0x10]
00000c  21fc              MOVS     r1,#0xfc
;;;434      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00000e  6011              STR      r1,[r2,#0]
000010  6902              LDR      r2,[r0,#0x10]
;;;435      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000012  6051              STR      r1,[r2,#4]
000014  6902              LDR      r2,[r0,#0x10]
;;;436      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000016  6091              STR      r1,[r2,#8]
000018  6902              LDR      r2,[r0,#0x10]
;;;437      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00001a  60d1              STR      r1,[r2,#0xc]
00001c  6942              LDR      r2,[r0,#0x14]
;;;438      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00001e  6011              STR      r1,[r2,#0]
000020  6942              LDR      r2,[r0,#0x14]
;;;439      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000022  6051              STR      r1,[r2,#4]
000024  6942              LDR      r2,[r0,#0x14]
;;;440      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
000026  6091              STR      r1,[r2,#8]
000028  6942              LDR      r2,[r0,#0x14]
;;;441      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00002a  60d1              STR      r1,[r2,#0xc]
00002c  6982              LDR      r2,[r0,#0x18]
;;;442      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00002e  6011              STR      r1,[r2,#0]
000030  6982              LDR      r2,[r0,#0x18]
;;;443      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000032  6051              STR      r1,[r2,#4]
000034  6982              LDR      r2,[r0,#0x18]
;;;444      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000036  6091              STR      r1,[r2,#8]
000038  6980              LDR      r0,[r0,#0x18]
;;;445    }
00003a  60c1              STR      r1,[r0,#0xc]
00003c  4770              BX       lr
;;;446    
                          ENDP


                          AREA ||i.FSMC_NORSRAMCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NORSRAMCmd PROC
;;;461    void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState)
;;;462    {
000000  f04ff04f          MOV      r2,#0xa0000000
000004  eb02eb02          ADD      r0,r2,r0,LSL #2
;;;463      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;464      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;465      
;;;466      if (NewState != DISABLE)
000008  2900              CMP      r1,#0
;;;467      {
;;;468        /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
;;;469        FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
00000a  6801              LDR      r1,[r0,#0]
00000c  d002              BEQ      |L10.20|
00000e  f041f041          ORR      r1,r1,#1
000012  e001              B        |L10.24|
                  |L10.20|
;;;470      }
;;;471      else
;;;472      {
;;;473        /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
;;;474        FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
000014  4a01              LDR      r2,|L10.28|
000016  4011              ANDS     r1,r1,r2
                  |L10.24|
000018  6001              STR      r1,[r0,#0]            ;469
;;;475      }
;;;476    }
00001a  4770              BX       lr
;;;477    
                          ENDP

                  |L10.28|
00001c  000ffffe          DCD      0x000ffffe

                          AREA ||i.FSMC_NANDCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NANDCmd PROC
;;;490    void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState)
;;;491    {
000000  f04ff04f          MOV      r2,#0xa0000000
;;;492      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;493      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;494      
;;;495      if (NewState != DISABLE)
000004  b151              CBZ      r1,|L11.28|
;;;496      {
;;;497        /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
;;;498        if(FSMC_Bank == FSMC_Bank2_NAND)
000006  2810              CMP      r0,#0x10
000008  d103              BNE      |L11.18|
;;;499        {
;;;500          FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
00000a  6e10              LDR      r0,[r2,#0x60]
00000c  f040f040          ORR      r0,r0,#4
000010  e009              B        |L11.38|
                  |L11.18|
;;;501        }
;;;502        else
;;;503        {
;;;504          FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
000012  f852f852          LDR      r0,[r2,#0x80]!
000016  f040f040          ORR      r0,r0,#4
00001a  e009              B        |L11.48|
                  |L11.28|
00001c  4905              LDR      r1,|L11.52|
;;;505        }
;;;506      }
;;;507      else
;;;508      {
;;;509        /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
;;;510        if(FSMC_Bank == FSMC_Bank2_NAND)
00001e  2810              CMP      r0,#0x10
000020  d103              BNE      |L11.42|
;;;511        {
;;;512          FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
000022  6e10              LDR      r0,[r2,#0x60]
000024  4008              ANDS     r0,r0,r1
                  |L11.38|
000026  6610              STR      r0,[r2,#0x60]         ;500
;;;513        }
;;;514        else
;;;515        {
;;;516          FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
;;;517        }
;;;518      }
;;;519    }
000028  4770              BX       lr
                  |L11.42|
00002a  f852f852          LDR      r0,[r2,#0x80]!        ;516
00002e  4008              ANDS     r0,r0,r1              ;516
                  |L11.48|
000030  6010              STR      r0,[r2,#0]            ;504
000032  4770              BX       lr
;;;520    
                          ENDP

                  |L11.52|
000034  000ffffb          DCD      0x000ffffb

                          AREA ||i.FSMC_PCCARDCmd||, CODE, READONLY, ALIGN=2

                  FSMC_PCCARDCmd PROC
;;;532      
;;;533      if (NewState != DISABLE)
000000  4905              LDR      r1,|L12.24|
000002  2800              CMP      r0,#0
;;;534      {
;;;535        /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
;;;536        FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
000004  6808              LDR      r0,[r1,#0]
000006  d002              BEQ      |L12.14|
000008  f040f040          ORR      r0,r0,#4
00000c  e001              B        |L12.18|
                  |L12.14|
;;;537      }
;;;538      else
;;;539      {
;;;540        /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
;;;541        FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
00000e  4a03              LDR      r2,|L12.28|
000010  4010              ANDS     r0,r0,r2
                  |L12.18|
000012  6008              STR      r0,[r1,#0]            ;536
;;;542      }
;;;543    }
000014  4770              BX       lr
;;;544    
                          ENDP

000016  0000              DCW      0x0000
                  |L12.24|
000018  a00000a0          DCD      0xa00000a0
                  |L12.28|
00001c  000ffffb          DCD      0x000ffffb

                          AREA ||i.FSMC_NANDECCCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NANDECCCmd PROC
;;;557    void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState)
;;;558    {
000000  f04ff04f          MOV      r2,#0xa0000000
;;;559      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;560      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;561      
;;;562      if (NewState != DISABLE)
000004  b151              CBZ      r1,|L13.28|
;;;563      {
;;;564        /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
;;;565        if(FSMC_Bank == FSMC_Bank2_NAND)
000006  2810              CMP      r0,#0x10
000008  d103              BNE      |L13.18|
;;;566        {
;;;567          FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
00000a  6e10              LDR      r0,[r2,#0x60]
00000c  f040f040          ORR      r0,r0,#0x40
000010  e009              B        |L13.38|
                  |L13.18|
;;;568        }
;;;569        else
;;;570        {
;;;571          FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
000012  f852f852          LDR      r0,[r2,#0x80]!
000016  f040f040          ORR      r0,r0,#0x40
00001a  e009              B        |L13.48|
                  |L13.28|
00001c  4905              LDR      r1,|L13.52|
;;;572        }
;;;573      }
;;;574      else
;;;575      {
;;;576        /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
;;;577        if(FSMC_Bank == FSMC_Bank2_NAND)
00001e  2810              CMP      r0,#0x10
000020  d103              BNE      |L13.42|
;;;578        {
;;;579          FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
000022  6e10              LDR      r0,[r2,#0x60]
000024  4008              ANDS     r0,r0,r1
                  |L13.38|
000026  6610              STR      r0,[r2,#0x60]         ;567
;;;580        }
;;;581        else
;;;582        {
;;;583          FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
;;;584        }
;;;585      }
;;;586    }
000028  4770              BX       lr
                  |L13.42|
00002a  f852f852          LDR      r0,[r2,#0x80]!        ;583
00002e  4008              ANDS     r0,r0,r1              ;583
                  |L13.48|
000030  6010              STR      r0,[r2,#0]            ;571
000032  4770              BX       lr
;;;587    
                          ENDP

                  |L13.52|
000034  000fffbf          DCD      0x000fffbf

                          AREA ||i.FSMC_GetECC||, CODE, READONLY, ALIGN=1

                  FSMC_GetECC PROC
;;;598    u32 FSMC_GetECC(u32 FSMC_Bank)
;;;599    {
000000  f04ff04f          MOV      r1,#0xa0000000
;;;600      u32 eccval = 0x00000000;
;;;601      
;;;602      if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2810              CMP      r0,#0x10
000006  d101              BNE      |L14.12|
;;;603      {
;;;604        /* Get the ECCR2 register value */
;;;605        eccval = FSMC_Bank2->ECCR2;
000008  6f48              LDR      r0,[r1,#0x74]
;;;606      }
;;;607      else
;;;608      {
;;;609        /* Get the ECCR3 register value */
;;;610        eccval = FSMC_Bank3->ECCR3;
;;;611      }
;;;612      /* Return the error correction code value */
;;;613      return(eccval);
;;;614    }
00000a  4770              BX       lr
                  |L14.12|
00000c  f8d1f8d1          LDR      r0,[r1,#0x94]         ;610
000010  4770              BX       lr
;;;615    
                          ENDP


                          AREA ||i.FSMC_ITConfig||, CODE, READONLY, ALIGN=1

                  FSMC_ITConfig PROC
;;;635    void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState)
;;;636    {
000000  b510              PUSH     {r4,lr}
000002  f44ff44f          MOV      r4,#0x100
000006  f04ff04f          MOV      r3,#0xa0000000

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