📄 stm32f10x_fsmc.txt
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;;;252 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
;;;253 tmppcr = (u32)FSMC_NANDInitStruct->FSMC_Waitfeature |
000002 e9d0e9d0 LDRD r2,r3,[r0,#4]
000006 431a ORRS r2,r2,r3
000008 e9d0e9d0 LDRD r4,r3,[r0,#0x10]
00000c 68c1 LDR r1,[r0,#0xc]
00000e 4321 ORRS r1,r1,r4
000010 430a ORRS r2,r2,r1
000012 431a ORRS r2,r2,r3
000014 e9d0e9d0 LDRD r1,r3,[r0,#0x18]
000018 ea42ea42 ORR r2,r2,r1,LSL #9
;;;254 PCR_MemoryType_NAND |
;;;255 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
;;;256 FSMC_NANDInitStruct->FSMC_ECC |
;;;257 FSMC_NANDInitStruct->FSMC_ECCPageSize |
;;;258 FSMC_NANDInitStruct->FSMC_AddressLowMapping |
;;;259 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
;;;260 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
;;;261
;;;262 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
;;;263 tmppmem = (u32)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
00001c 6a01 LDR r1,[r0,#0x20]
00001e ea42ea42 ORR r2,r2,r3,LSL #13 ;253
000022 e891e891 LDM r1,{r3-r5}
;;;264 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;265 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;266 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;267
;;;268 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;269 tmppatt = (u32)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
000026 68ce LDR r6,[r1,#0xc]
000028 042d LSLS r5,r5,#16 ;263
00002a ea43ea43 ORR r3,r3,r4,LSL #8 ;263
00002e 6a41 LDR r1,[r0,#0x24]
000030 ea45ea45 ORR r5,r5,r6,LSL #24 ;263
000034 432b ORRS r3,r3,r5 ;263
000036 e891e891 LDM r1,{r4-r6}
00003a ea44ea44 ORR r4,r4,r5,LSL #8
00003e 0435 LSLS r5,r6,#16
000040 68c9 LDR r1,[r1,#0xc]
;;;270 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;271 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;272 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;273
;;;274 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
000042 6806 LDR r6,[r0,#0]
000044 ea45ea45 ORR r1,r5,r1,LSL #24 ;269
000048 430c ORRS r4,r4,r1 ;269
00004a f042f042 ORR r2,r2,#8 ;253
00004e f04ff04f MOV r0,#0xa0000000
000052 2e10 CMP r6,#0x10
000054 d103 BNE |L5.94|
;;;275 {
;;;276 /* FSMC_Bank2_NAND registers configuration */
;;;277 FSMC_Bank2->PCR2 = tmppcr;
000056 6602 STR r2,[r0,#0x60]
;;;278 FSMC_Bank2->PMEM2 = tmppmem;
000058 6683 STR r3,[r0,#0x68]
;;;279 FSMC_Bank2->PATT2 = tmppatt;
00005a 66c4 STR r4,[r0,#0x6c]
;;;280 }
;;;281 else
;;;282 {
;;;283 /* FSMC_Bank3_NAND registers configuration */
;;;284 FSMC_Bank3->PCR3 = tmppcr;
;;;285 FSMC_Bank3->PMEM3 = tmppmem;
;;;286 FSMC_Bank3->PATT3 = tmppatt;
;;;287 }
;;;288 }
00005c bd70 POP {r4-r6,pc}
|L5.94|
00005e f840f840 STR r2,[r0,#0x80]! ;284
000062 6083 STR r3,[r0,#8] ;285
000064 60c4 STR r4,[r0,#0xc] ;286
000066 bd70 POP {r4-r6,pc}
;;;289
ENDP
AREA ||i.FSMC_PCCARDInit||, CODE, READONLY, ALIGN=2
FSMC_PCCARDInit PROC
;;;300 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
;;;301 {
000000 b570 PUSH {r4-r6,lr}
;;;302 /* Check the parameters */
;;;303 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
;;;304 assert_param(IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_PCCARDInitStruct->FSMC_AddressLowMapping));
;;;305 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
;;;306 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
;;;307
;;;308
;;;309 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;310 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;311 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;312 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;313
;;;314 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;315 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;316 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;317 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;318
;;;319 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
;;;320 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
;;;321 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
;;;322 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
;;;323
;;;324 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
;;;325 FSMC_Bank4->PCR4 = (u32)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
000002 e890e890 LDM r0,{r1-r3}
000006 68c4 LDR r4,[r0,#0xc]
000008 4311 ORRS r1,r1,r2
00000a 025b LSLS r3,r3,#9
00000c ea43ea43 ORR r3,r3,r4,LSL #13
000010 4a13 LDR r2,|L6.96|
000012 4319 ORRS r1,r1,r3
000014 6011 STR r1,[r2,#0]
;;;326 FSMC_PCCARDInitStruct->FSMC_AddressLowMapping |
;;;327 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
;;;328 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
;;;329
;;;330 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
;;;331 FSMC_Bank4->PMEM4 = (u32)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
000016 6901 LDR r1,[r0,#0x10]
000018 e9d1e9d1 LDRD r3,r4,[r1,#4]
00001c 680d LDR r5,[r1,#0]
00001e 68ce LDR r6,[r1,#0xc]
000020 0424 LSLS r4,r4,#16
000022 ea45ea45 ORR r1,r5,r3,LSL #8
000026 ea44ea44 ORR r3,r4,r6,LSL #24
00002a 4319 ORRS r1,r1,r3
00002c 6091 STR r1,[r2,#8]
;;;332 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;333 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;334 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;335
;;;336 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;337 FSMC_Bank4->PATT4 = (u32)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00002e 6941 LDR r1,[r0,#0x14]
000030 e9d1e9d1 LDRD r3,r4,[r1,#4]
000034 680d LDR r5,[r1,#0]
000036 68ce LDR r6,[r1,#0xc]
000038 0424 LSLS r4,r4,#16
00003a ea45ea45 ORR r1,r5,r3,LSL #8
00003e ea44ea44 ORR r3,r4,r6,LSL #24
000042 4319 ORRS r1,r1,r3
000044 60d1 STR r1,[r2,#0xc]
;;;338 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;339 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;340 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;341
;;;342 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
;;;343 FSMC_Bank4->PIO4 = (u32)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
000046 6980 LDR r0,[r0,#0x18]
000048 e9d0e9d0 LDRD r3,r1,[r0,#4]
00004c 6804 LDR r4,[r0,#0]
00004e 68c5 LDR r5,[r0,#0xc]
000050 0409 LSLS r1,r1,#16
000052 ea44ea44 ORR r0,r4,r3,LSL #8
000056 ea41ea41 ORR r1,r1,r5,LSL #24
00005a 4308 ORRS r0,r0,r1
00005c 6110 STR r0,[r2,#0x10]
;;;344 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;345 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;346 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;347 }
00005e bd70 POP {r4-r6,pc}
;;;348
ENDP
|L6.96|
000060 a00000a0 DCD 0xa00000a0
AREA ||i.FSMC_NORSRAMStructInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMStructInit PROC
;;;357 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
;;;358 {
000000 b510 PUSH {r4,lr}
;;;359 /* Reset NOR/SRAM Init structure parameters values */
;;;360 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
000002 2100 MOVS r1,#0
;;;361 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
000004 2202 MOVS r2,#2
;;;362 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
000006 e9c0e9c0 STRD r1,r2,[r0,#0]
;;;363 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00000a 6081 STR r1,[r0,#8]
;;;364 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00000c 60c1 STR r1,[r0,#0xc]
;;;365 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00000e 6101 STR r1,[r0,#0x10]
;;;366 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
000010 6141 STR r1,[r0,#0x14]
;;;367 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
000012 6181 STR r1,[r0,#0x18]
;;;368 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
000014 02d2 LSLS r2,r2,#11
;;;369 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
000016 e9c0e9c0 STRD r1,r2,[r0,#0x1c]
00001a 0052 LSLS r2,r2,#1
;;;370 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
;;;371 FSMC_NORSRAMInitStruct->FSMC_AsyncWait = FSMC_AsyncWait_Disable;
00001c e9c0e9c0 STRD r2,r1,[r0,#0x24]
;;;372 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
000020 62c1 STR r1,[r0,#0x2c]
;;;373 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
000022 6301 STR r1,[r0,#0x30]
000024 6b43 LDR r3,[r0,#0x34]
000026 220f MOVS r2,#0xf
;;;374 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
000028 601a STR r2,[r3,#0]
00002a 6b43 LDR r3,[r0,#0x34]
;;;375 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00002c 24ff MOVS r4,#0xff
00002e 605a STR r2,[r3,#4]
000030 6b43 LDR r3,[r0,#0x34]
;;;376 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
000032 609c STR r4,[r3,#8]
000034 6b43 LDR r3,[r0,#0x34]
;;;377 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
000036 60da STR r2,[r3,#0xc]
000038 6b43 LDR r3,[r0,#0x34]
;;;378 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
00003a 611a STR r2,[r3,#0x10]
00003c 6b43 LDR r3,[r0,#0x34]
;;;379 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00003e 615a STR r2,[r3,#0x14]
000040 6b43 LDR r3,[r0,#0x34]
;;;380 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
000042 6199 STR r1,[r3,#0x18]
000044 6b83 LDR r3,[r0,#0x38]
;;;381 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
000046 601a STR r2,[r3,#0]
000048 6b83 LDR r3,[r0,#0x38]
;;;382 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00004a 605a STR r2,[r3,#4]
00004c 6b83 LDR r3,[r0,#0x38]
;;;383 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00004e 609c STR r4,[r3,#8]
000050 6b83 LDR r3,[r0,#0x38]
;;;384 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
000052 60da STR r2,[r3,#0xc]
000054 6b83 LDR r3,[r0,#0x38]
;;;385 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
000056 611a STR r2,[r3,#0x10]
000058 6b83 LDR r3,[r0,#0x38]
;;;386 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00005a 615a STR r2,[r3,#0x14]
00005c 6b80 LDR r0,[r0,#0x38]
;;;387 }
00005e 6181 STR r1,[r0,#0x18]
000060 bd10 POP {r4,pc}
;;;388
ENDP
AREA ||i.FSMC_NANDStructInit||, CODE, READONLY, ALIGN=1
FSMC_NANDStructInit PROC
;;;399 /* Reset NAND Init structure parameters values */
;;;400 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
000000 2110 MOVS r1,#0x10
;;;401 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000002 6001 STR r1,[r0,#0]
000004 2100 MOVS r1,#0
;;;402 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
000006 6041 STR r1,[r0,#4]
;;;403 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
000008 6081 STR r1,[r0,#8]
;;;404 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
00000a 60c1 STR r1,[r0,#0xc]
;;;405 FSMC_NANDInitStruct->FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
00000c 6101 STR r1,[r0,#0x10]
;;;406 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
00000e 6141 STR r1,[r0,#0x14]
;;;407 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
000010 6181 STR r1,[r0,#0x18]
;;;408 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000012 61c1 STR r1,[r0,#0x1c]
000014 6a02 LDR r2,[r0,#0x20]
000016 21fc MOVS r1,#0xfc
;;;409 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000018 6011 STR r1,[r2,#0]
00001a 6a02 LDR r2,[r0,#0x20]
;;;410 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00001c 6051 STR r1,[r2,#4]
00001e 6a02 LDR r2,[r0,#0x20]
;;;411 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000020 6091 STR r1,[r2,#8]
000022 6a02 LDR r2,[r0,#0x20]
;;;412 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000024 60d1 STR r1,[r2,#0xc]
000026 6a42 LDR r2,[r0,#0x24]
;;;413 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000028 6011 STR r1,[r2,#0]
00002a 6a42 LDR r2,[r0,#0x24]
;;;414 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00002c 6051 STR r1,[r2,#4]
00002e 6a42 LDR r2,[r0,#0x24]
;;;415 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000030 6091 STR r1,[r2,#8]
000032 6a40 LDR r0,[r0,#0x24]
;;;416 }
000034 60c1 STR r1,[r0,#0xc]
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