📄 stm32f10x_fsmc.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_fsmc.o --depend=.\Obj\stm32f10x_fsmc.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_fsmc.crf ..\..\..\FWLib\library\src\stm32f10x_fsmc.c]
THUMB
AREA ||i.FSMC_NORSRAMDeInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMDeInit PROC
;;;53 void FSMC_NORSRAMDeInit(u32 FSMC_Bank)
;;;54 {
000000 f04ff04f MOV r2,#0xa0000000
000004 eb02eb02 ADD r1,r2,r0,LSL #2
;;;55 /* Check the parameter */
;;;56 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;57
;;;58 /* FSMC_Bank1_NORSRAM1 */
;;;59 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
000008 b918 CBNZ r0,|L1.18|
;;;60 {
;;;61 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
00000a f243f243 MOV r0,#0x30db
00000e 6010 STR r0,[r2,#0]
000010 e002 B |L1.24|
|L1.18|
;;;62 }
;;;63 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
;;;64 else
;;;65 {
;;;66 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
000012 f243f243 MOV r0,#0x30d2
000016 6008 STR r0,[r1,#0]
|L1.24|
;;;67 }
;;;68
;;;69 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
000018 f06ff06f MVN r0,#0xf0000000
00001c 6048 STR r0,[r1,#4]
;;;70 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
00001e f8c1f8c1 STR r0,[r1,#0x104]
;;;71 }
000022 4770 BX lr
;;;72
ENDP
AREA ||i.FSMC_NANDDeInit||, CODE, READONLY, ALIGN=1
FSMC_NANDDeInit PROC
;;;84 void FSMC_NANDDeInit(u32 FSMC_Bank)
;;;85 {
000000 b510 PUSH {r4,lr}
000002 2418 MOVS r4,#0x18
000004 2340 MOVS r3,#0x40
000006 f04ff04f MOV r1,#0xa0000000
00000a f04ff04f MOV r2,#0xfcfcfcfc
;;;86 /* Check the parameter */
;;;87 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;88
;;;89 if(FSMC_Bank == FSMC_Bank2_NAND)
00000e 2810 CMP r0,#0x10
000010 d104 BNE |L2.28|
;;;90 {
;;;91 /* Set the FSMC_Bank2 registers to their reset values */
;;;92 FSMC_Bank2->PCR2 = 0x00000018;
000012 660c STR r4,[r1,#0x60]
;;;93 FSMC_Bank2->SR2 = 0x00000040;
000014 664b STR r3,[r1,#0x64]
;;;94 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
000016 668a STR r2,[r1,#0x68]
;;;95 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
000018 66ca STR r2,[r1,#0x6c]
;;;96 }
;;;97 /* FSMC_Bank3_NAND */
;;;98 else
;;;99 {
;;;100 /* Set the FSMC_Bank3 registers to their reset values */
;;;101 FSMC_Bank3->PCR3 = 0x00000018;
;;;102 FSMC_Bank3->SR3 = 0x00000040;
;;;103 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
;;;104 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
;;;105 }
;;;106 }
00001a bd10 POP {r4,pc}
|L2.28|
00001c f841f841 STR r4,[r1,#0x80]! ;101
000020 604b STR r3,[r1,#4] ;102
000022 608a STR r2,[r1,#8] ;103
000024 60ca STR r2,[r1,#0xc] ;104
000026 bd10 POP {r4,pc}
;;;107
ENDP
AREA ||i.FSMC_PCCARDDeInit||, CODE, READONLY, ALIGN=2
FSMC_PCCARDDeInit PROC
;;;118 /* Set the FSMC_Bank4 registers to their reset values */
;;;119 FSMC_Bank4->PCR4 = 0x00000018;
000000 4805 LDR r0,|L3.24|
000002 2118 MOVS r1,#0x18
000004 6001 STR r1,[r0,#0]
;;;120 FSMC_Bank4->SR4 = 0x00000000;
000006 2100 MOVS r1,#0
000008 6041 STR r1,[r0,#4]
;;;121 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
00000a f04ff04f MOV r1,#0xfcfcfcfc
00000e 6081 STR r1,[r0,#8]
;;;122 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
000010 60c1 STR r1,[r0,#0xc]
;;;123 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
000012 6101 STR r1,[r0,#0x10]
;;;124 }
000014 4770 BX lr
;;;125
ENDP
000016 0000 DCW 0x0000
|L3.24|
000018 a00000a0 DCD 0xa00000a0
AREA ||i.FSMC_NORSRAMInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMInit PROC
;;;136 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
;;;137 {
000000 b5f0 PUSH {r4-r7,lr}
;;;138 /* Check the parameters */
;;;139 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
;;;140 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
;;;141 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
;;;142 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
;;;143 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
;;;144 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
;;;145 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
;;;146 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
;;;147 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
;;;148 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
;;;149 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
;;;150 assert_param(IS_FSMC_ASYNC_WAIT(FSMC_NORSRAMInitStruct->FSMC_AsyncWait));
;;;151 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
;;;152 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
;;;153 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
;;;154 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
;;;155 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
;;;156 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
;;;157 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
;;;158 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
;;;159
;;;160 /* Bank1 NOR/SRAM control register configuration */
;;;161 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
000002 e9d0e9d0 LDRD r3,r2,[r0,#8]
000006 6841 LDR r1,[r0,#4]
000008 4319 ORRS r1,r1,r3
00000a e9d0e9d0 LDRD r4,r3,[r0,#0x10]
00000e 4322 ORRS r2,r2,r4
000010 4311 ORRS r1,r1,r2
000012 4319 ORRS r1,r1,r3
000014 e9d0e9d0 LDRD r2,r3,[r0,#0x18]
000018 4311 ORRS r1,r1,r2
00001a 4319 ORRS r1,r1,r3
00001c e9d0e9d0 LDRD r2,r3,[r0,#0x20]
000020 4311 ORRS r1,r1,r2
000022 4319 ORRS r1,r1,r3
000024 e9d0e9d0 LDRD r2,r3,[r0,#0x28]
000028 4311 ORRS r1,r1,r2
00002a 4319 ORRS r1,r1,r3
00002c 6b02 LDR r2,[r0,#0x30]
00002e 6803 LDR r3,[r0,#0]
000030 4311 ORRS r1,r1,r2
000032 f04ff04f MOV r2,#0xa0000000
000036 f842f842 STR r1,[r2,r3,LSL #2]
;;;162 (u32)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
;;;163 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
;;;164 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
;;;165 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
;;;166 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
;;;167 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
;;;168 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
;;;169 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
;;;170 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
;;;171 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
;;;172 FSMC_NORSRAMInitStruct->FSMC_AsyncWait |
;;;173 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
;;;174
;;;175 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
00003a 6881 LDR r1,[r0,#8]
00003c 2908 CMP r1,#8
00003e d106 BNE |L4.78|
;;;176 {
;;;177 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (u32)BCR_FACCEN_Set;
000040 6801 LDR r1,[r0,#0]
000042 eb02eb02 ADD r1,r2,r1,LSL #2
000046 680b LDR r3,[r1,#0]
000048 f043f043 ORR r3,r3,#0x40
00004c 600b STR r3,[r1,#0]
|L4.78|
;;;178 }
;;;179
;;;180 /* Bank1 NOR/SRAM timing register configuration */
;;;181 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
00004e 6b41 LDR r1,[r0,#0x34]
000050 e9d1e9d1 LDRD r3,r4,[r1,#4]
000054 e9d1e9d1 LDRD r5,r6,[r1,#0xc]
000058 680f LDR r7,[r1,#0]
00005a 0224 LSLS r4,r4,#8
00005c ea47ea47 ORR r3,r7,r3,LSL #4
000060 ea44ea44 ORR r4,r4,r5,LSL #16
000064 4323 ORRS r3,r3,r4
000066 e9d1e9d1 LDRD r7,r4,[r1,#0x14]
00006a ea43ea43 ORR r3,r3,r6,LSL #20
00006e ea43ea43 ORR r1,r3,r7,LSL #24
000072 6803 LDR r3,[r0,#0]
000074 4321 ORRS r1,r1,r4
000076 eb02eb02 ADD r3,r2,r3,LSL #2
00007a 6059 STR r1,[r3,#4]
;;;182 (u32)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
;;;183 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
;;;184 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;185 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
;;;186 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
;;;187 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
;;;188 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
;;;189
;;;190
;;;191
;;;192 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
;;;193 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
00007c 6a81 LDR r1,[r0,#0x28]
00007e f5b1f5b1 CMP r1,#0x4000
000082 d114 BNE |L4.174|
;;;194 {
;;;195 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
;;;196 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
;;;197 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
;;;198 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration));
;;;199 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
;;;200 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
;;;201 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
;;;202
;;;203 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
000084 6b81 LDR r1,[r0,#0x38]
000086 6800 LDR r0,[r0,#0]
000088 e9d1e9d1 LDRD r3,r4,[r1,#4]
00008c e9d1e9d1 LDRD r5,r6,[r1,#0xc]
000090 680f LDR r7,[r1,#0]
000092 0224 LSLS r4,r4,#8
000094 ea47ea47 ORR r3,r7,r3,LSL #4
000098 ea44ea44 ORR r4,r4,r5,LSL #16
00009c 4323 ORRS r3,r3,r4
00009e e9d1e9d1 LDRD r7,r4,[r1,#0x14]
0000a2 ea43ea43 ORR r3,r3,r6,LSL #20
0000a6 ea43ea43 ORR r1,r3,r7,LSL #24
0000aa 4321 ORRS r1,r1,r4
0000ac e002 B |L4.180|
|L4.174|
;;;204 (u32)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
;;;205 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
;;;206 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;207 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
;;;208 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
;;;209 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
;;;210 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
;;;211 }
;;;212 else
;;;213 {
;;;214 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
0000ae 6800 LDR r0,[r0,#0]
0000b0 f06ff06f MVN r1,#0xf0000000
|L4.180|
0000b4 eb02eb02 ADD r0,r2,r0,LSL #2 ;203
0000b8 f8c0f8c0 STR r1,[r0,#0x104] ;203
;;;215 }
;;;216 }
0000bc bdf0 POP {r4-r7,pc}
;;;217
ENDP
AREA ||i.FSMC_NANDInit||, CODE, READONLY, ALIGN=1
FSMC_NANDInit PROC
;;;228 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
;;;229 {
000000 b570 PUSH {r4-r6,lr}
;;;230 u32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
;;;231
;;;232 /* Check the parameters */
;;;233 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
;;;234 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
;;;235 assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
;;;236 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
;;;237 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
;;;238 assert_param( IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_NANDInitStruct->FSMC_AddressLowMapping));
;;;239 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
;;;240 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
;;;241
;;;242 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;243 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;244 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;245 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;246
;;;247 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;248 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;249 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;250 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;251
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