📄 stm32f10x_i2c.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_i2c.o --depend=.\Obj\stm32f10x_i2c.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_i2c.crf ..\..\..\FWLib\library\src\stm32f10x_i2c.c]
THUMB
AREA ||i.I2C_DeInit||, CODE, READONLY, ALIGN=2
I2C_DeInit PROC
;;;113
;;;114 switch (*(u32*)&I2Cx)
000000 490a LDR r1,|L1.44|
000002 b510 PUSH {r4,lr}
000004 1840 ADDS r0,r0,r1
000006 d00d BEQ |L1.36|
000008 f5b0f5b0 CMP r0,#0x400
00000c d10d BNE |L1.42|
;;;115 {
;;;116 case I2C1_BASE:
;;;117 /* Enable I2C1 reset state */
;;;118 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
;;;119 /* Release I2C1 from reset state */
;;;120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
;;;121 break;
;;;122
;;;123 case I2C2_BASE:
;;;124 /* Enable I2C2 reset state */
;;;125 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
00000e 2101 MOVS r1,#1
000010 058c LSLS r4,r1,#22
|L1.18|
000012 4620 MOV r0,r4
000014 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;126 /* Release I2C2 from reset state */
;;;127 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
000018 4620 MOV r0,r4
00001a e8bde8bd POP {r4,lr}
00001e 2100 MOVS r1,#0
000020 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.36|
000024 2101 MOVS r1,#1 ;118
000026 054c LSLS r4,r1,#21 ;118
000028 e7f3 B |L1.18|
|L1.42|
;;;128 break;
;;;129
;;;130 default:
;;;131 break;
;;;132 }
;;;133 }
00002a bd10 POP {r4,pc}
;;;134
ENDP
|L1.44|
00002c bfffac00 DCD 0xbfffac00
AREA ||i.I2C_Init||, CODE, READONLY, ALIGN=2
I2C_Init PROC
;;;146 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
;;;147 {
000000 b570 PUSH {r4-r6,lr}
000002 4604 MOV r4,r0
;;;148 u16 tmpreg = 0, freqrange = 0;
;;;149 u16 result = 0x04;
;;;150 u32 pclk1 = 8000000;
;;;151 RCC_ClocksTypeDef rcc_clocks;
;;;152
;;;153 /* Check the parameters */
;;;154 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
;;;155 assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
;;;156 assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
;;;157 assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
;;;158 assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
;;;159 assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
;;;160 assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
;;;161
;;;162 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
;;;163 /* Get the I2Cx CR2 value */
;;;164 tmpreg = I2Cx->CR2;
000004 8880 LDRH r0,[r0,#4]
000006 b086 SUB sp,sp,#0x18 ;147
000008 460d MOV r5,r1 ;147
;;;165 /* Clear frequency FREQ[5:0] bits */
;;;166 tmpreg &= CR2_FREQ_Reset;
00000a f020f020 BIC r6,r0,#0x3f
;;;167 /* Get pclk1 frequency value */
;;;168 RCC_GetClocksFreq(&rcc_clocks);
00000e a801 ADD r0,sp,#4
000010 f7fff7ff BL RCC_GetClocksFreq
;;;169 pclk1 = rcc_clocks.PCLK1_Frequency;
;;;170 /* Set frequency bits depending on pclk1 value */
;;;171 freqrange = (u16)(pclk1 / 1000000);
000014 4925 LDR r1,|L2.172|
000016 9803 LDR r0,[sp,#0xc]
000018 fbb0fbb0 UDIV r1,r0,r1
00001c b289 UXTH r1,r1
;;;172 tmpreg |= freqrange;
00001e 430e ORRS r6,r6,r1
;;;173 /* Write to I2Cx CR2 */
;;;174 I2Cx->CR2 = tmpreg;
000020 80a6 STRH r6,[r4,#4]
;;;175
;;;176 /*---------------------------- I2Cx CCR Configuration ------------------------*/
;;;177 /* Disable the selected I2C peripheral to configure TRISE */
;;;178 I2Cx->CR1 &= CR1_PE_Reset;
000022 8822 LDRH r2,[r4,#0]
000024 f022f022 BIC r2,r2,#1
000028 8022 STRH r2,[r4,#0]
;;;179
;;;180 /* Reset tmpreg value */
;;;181 /* Clear F/S, DUTY and CCR[11:0] bits */
;;;182 tmpreg = 0;
;;;183
;;;184 /* Configure speed in standard mode */
;;;185 if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
00002a 4b21 LDR r3,|L2.176|
00002c 68ea LDR r2,[r5,#0xc]
00002e 429a CMP r2,r3
000030 d81c BHI |L2.108|
;;;186 {
;;;187 /* Standard mode speed calculate */
;;;188 result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
000032 0052 LSLS r2,r2,#1
000034 fbb0fbb0 UDIV r0,r0,r2
000038 b280 UXTH r0,r0
;;;189 /* Test if CCR value is under 0x4*/
;;;190 if (result < 0x04)
00003a 2804 CMP r0,#4
00003c d200 BCS |L2.64|
;;;191 {
;;;192 /* Set minimum allowed value */
;;;193 result = 0x04;
00003e 2004 MOVS r0,#4
|L2.64|
;;;194 }
;;;195 /* Set speed value for standard mode */
;;;196 tmpreg |= result;
;;;197 /* Set Maximum Rise Time for standard mode */
;;;198 I2Cx->TRISE = freqrange + 1;
000040 1c49 ADDS r1,r1,#1
000042 8421 STRH r1,[r4,#0x20]
;;;199 }
;;;200 /* Configure speed in fast mode */
;;;201 else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
;;;202 {
;;;203 if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
;;;204 {
;;;205 /* Fast mode speed calculate: Tlow/Thigh = 2 */
;;;206 result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
;;;207 }
;;;208 else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
;;;209 {
;;;210 /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
;;;211 result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
;;;212 /* Set DUTY bit */
;;;213 result |= I2C_DutyCycle_16_9;
;;;214 }
;;;215 /* Test if CCR value is under 0x1*/
;;;216 if ((result & CCR_CCR_Set) == 0)
;;;217 {
;;;218 /* Set minimum allowed value */
;;;219 result |= (u16)0x0001;
;;;220 }
;;;221 /* Set speed value and set F/S bit for fast mode */
;;;222 tmpreg |= result | CCR_FS_Set;
;;;223 /* Set Maximum Rise Time for fast mode */
;;;224 I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1);
;;;225 }
;;;226 /* Write to I2Cx CCR */
;;;227 I2Cx->CCR = tmpreg;
000044 83a0 STRH r0,[r4,#0x1c]
;;;228
;;;229 /* Enable the selected I2C peripheral */
;;;230 I2Cx->CR1 |= CR1_PE_Set;
000046 8820 LDRH r0,[r4,#0]
000048 f040f040 ORR r0,r0,#1
00004c 8020 STRH r0,[r4,#0]
;;;231
;;;232 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
;;;233 /* Get the I2Cx CR1 value */
;;;234 tmpreg = I2Cx->CR1;
00004e 8820 LDRH r0,[r4,#0]
;;;235 /* Clear ACK, SMBTYPE and SMBUS bits */
;;;236 tmpreg &= CR1_CLEAR_Mask;
000050 f64ff64f MOV r1,#0xfbf5
000054 4008 ANDS r0,r0,r1
;;;237 /* Configure I2Cx: mode and acknowledgement */
;;;238 /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
;;;239 /* Set ACK bit according to I2C_Ack value */
;;;240 tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
000056 8829 LDRH r1,[r5,#0]
000058 88ea LDRH r2,[r5,#6]
00005a 4311 ORRS r1,r1,r2
00005c 4301 ORRS r1,r1,r0
;;;241 /* Write to I2Cx CR1 */
;;;242 I2Cx->CR1 = tmpreg;
00005e 8021 STRH r1,[r4,#0]
;;;243
;;;244 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
;;;245 /* Set I2Cx Own Address1 and acknowledged address */
;;;246 I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
000060 8928 LDRH r0,[r5,#8]
000062 88a9 LDRH r1,[r5,#4]
000064 4308 ORRS r0,r0,r1
000066 8120 STRH r0,[r4,#8]
;;;247 }
000068 b006 ADD sp,sp,#0x18
00006a bd70 POP {r4-r6,pc}
|L2.108|
00006c 886b LDRH r3,[r5,#2] ;203
00006e f5a3f5a3 SUB r6,r3,#0xbf00 ;203
000072 3eff SUBS r6,r6,#0xff ;203
000074 d105 BNE |L2.130|
000076 eb02eb02 ADD r2,r2,r2,LSL #1 ;206
00007a fbb0fbb0 UDIV r0,r0,r2 ;206
00007e b280 UXTH r0,r0 ;206
000080 e006 B |L2.144|
|L2.130|
000082 2319 MOVS r3,#0x19 ;211
000084 435a MULS r2,r3,r2 ;211
000086 fbb0fbb0 UDIV r0,r0,r2 ;211
00008a b280 UXTH r0,r0 ;211
00008c f440f440 ORR r0,r0,#0x4000 ;213
|L2.144|
000090 0502 LSLS r2,r0,#20 ;216
000092 d101 BNE |L2.152|
000094 f040f040 ORR r0,r0,#1 ;219
|L2.152|
000098 f44ff44f MOV r2,#0x12c ;224
00009c 4351 MULS r1,r2,r1 ;224
00009e f44ff44f MOV r2,#0x3e8 ;224
0000a2 fbb1fbb1 UDIV r1,r1,r2 ;224
0000a6 f440f440 ORR r0,r0,#0x8000 ;222
0000aa e7c9 B |L2.64|
;;;248
ENDP
|L2.172|
0000ac 000f4240 DCD 0x000f4240
|L2.176|
0000b0 000186a0 DCD 0x000186a0
AREA ||i.I2C_StructInit||, CODE, READONLY, ALIGN=1
I2C_StructInit PROC
;;;260 /* Initialize the I2C_Mode member */
;;;261 I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
000000 2100 MOVS r1,#0
000002 8001 STRH r1,[r0,#0]
;;;262
;;;263 /* Initialize the I2C_DutyCycle member */
;;;264 I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
000004 f64bf64b MOV r2,#0xbfff
000008 8042 STRH r2,[r0,#2]
;;;265
;;;266 /* Initialize the I2C_OwnAddress1 member */
;;;267 I2C_InitStruct->I2C_OwnAddress1 = 0;
00000a 8081 STRH r1,[r0,#4]
;;;268
;;;269 /* Initialize the I2C_Ack member */
;;;270 I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
00000c 80c1 STRH r1,[r0,#6]
;;;271
;;;272 /* Initialize the I2C_AcknowledgedAddress member */
;;;273 I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00000e f44ff44f MOV r1,#0x4000
000012 8101 STRH r1,[r0,#8]
;;;274
;;;275 /* initialize the I2C_ClockSpeed member */
;;;276 I2C_InitStruct->I2C_ClockSpeed = 5000;
000014 f241f241 MOV r1,#0x1388
;;;277 }
000018 60c1 STR r1,[r0,#0xc]
00001a 4770 BX lr
;;;278
ENDP
AREA ||i.I2C_Cmd||, CODE, READONLY, ALIGN=1
I2C_Cmd PROC
;;;293
;;;294 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;295 {
;;;296 /* Enable the selected I2C peripheral */
;;;297 I2Cx->CR1 |= CR1_PE_Set;
000002 8801 LDRH r1,[r0,#0]
000004 d002 BEQ |L4.12|
000006 f041f041 ORR r1,r1,#1
00000a e001 B |L4.16|
|L4.12|
;;;298 }
;;;299 else
;;;300 {
;;;301 /* Disable the selected I2C peripheral */
;;;302 I2Cx->CR1 &= CR1_PE_Reset;
00000c f021f021 BIC r1,r1,#1
|L4.16|
000010 8001 STRH r1,[r0,#0] ;297
;;;303 }
;;;304 }
000012 4770 BX lr
;;;305
ENDP
AREA ||i.I2C_DMACmd||, CODE, READONLY, ALIGN=1
I2C_DMACmd PROC
;;;320
;;;321 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;322 {
;;;323 /* Enable the selected I2C DMA requests */
;;;324 I2Cx->CR2 |= CR2_DMAEN_Set;
000002 8881 LDRH r1,[r0,#4]
000004 d002 BEQ |L5.12|
000006 f441f441 ORR r1,r1,#0x800
00000a e001 B |L5.16|
|L5.12|
;;;325 }
;;;326 else
;;;327 {
;;;328 /* Disable the selected I2C DMA requests */
;;;329 I2Cx->CR2 &= CR2_DMAEN_Reset;
00000c f421f421 BIC r1,r1,#0x800
|L5.16|
000010 8081 STRH r1,[r0,#4] ;324
;;;330 }
;;;331 }
000012 4770 BX lr
;;;332
ENDP
AREA ||i.I2C_DMALastTransferCmd||, CODE, READONLY, ALIGN=1
I2C_DMALastTransferCmd PROC
;;;347
;;;348 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;349 {
;;;350 /* Next DMA transfer is the last transfer */
;;;351 I2Cx->CR2 |= CR2_LAST_Set;
000002 8881 LDRH r1,[r0,#4]
000004 d002 BEQ |L6.12|
000006 f441f441 ORR r1,r1,#0x1000
00000a e001 B |L6.16|
|L6.12|
;;;352 }
;;;353 else
;;;354 {
;;;355 /* Next DMA transfer is not the last transfer */
;;;356 I2Cx->CR2 &= CR2_LAST_Reset;
00000c f421f421 BIC r1,r1,#0x1000
|L6.16|
000010 8081 STRH r1,[r0,#4] ;351
;;;357 }
;;;358 }
000012 4770 BX lr
;;;359
ENDP
AREA ||i.I2C_GenerateSTART||, CODE, READONLY, ALIGN=1
I2C_GenerateSTART PROC
;;;374
;;;375 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;376 {
;;;377 /* Generate a START condition */
;;;378 I2Cx->CR1 |= CR1_START_Set;
000002 8801 LDRH r1,[r0,#0]
000004 d002 BEQ |L7.12|
000006 f441f441 ORR r1,r1,#0x100
00000a e001 B |L7.16|
|L7.12|
;;;379 }
;;;380 else
;;;381 {
;;;382 /* Disable the START condition generation */
;;;383 I2Cx->CR1 &= CR1_START_Reset;
00000c f421f421 BIC r1,r1,#0x100
|L7.16|
000010 8001 STRH r1,[r0,#0] ;378
;;;384 }
;;;385 }
000012 4770 BX lr
;;;386
ENDP
AREA ||i.I2C_GenerateSTOP||, CODE, READONLY, ALIGN=1
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