📄 stm32f10x_dma.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_dma.o --depend=.\Obj\stm32f10x_dma.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_dma.crf ..\..\..\FWLib\library\src\stm32f10x_dma.c]
THUMB
AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2
DMA_DeInit PROC
;;;68 /* Disable the selected DMAy Channelx */
;;;69 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
000000 6802 LDR r2,[r0,#0]
;;;70
;;;71 /* Reset DMAy Channelx control register */
;;;72 DMAy_Channelx->CCR = 0;
000002 2100 MOVS r1,#0
000004 f022f022 BIC r2,r2,#1 ;69
000008 6002 STR r2,[r0,#0] ;69
00000a 6001 STR r1,[r0,#0]
;;;73
;;;74 /* Reset DMAy Channelx remaining bytes register */
;;;75 DMAy_Channelx->CNDTR = 0;
00000c 6041 STR r1,[r0,#4]
;;;76
;;;77 /* Reset DMAy Channelx peripheral address register */
;;;78 DMAy_Channelx->CPAR = 0;
00000e 6081 STR r1,[r0,#8]
;;;79
;;;80 /* Reset DMAy Channelx memory address register */
;;;81 DMAy_Channelx->CMAR = 0;
000010 60c1 STR r1,[r0,#0xc]
;;;82
;;;83 switch (*(u32*)&DMAy_Channelx)
000012 4b30 LDR r3,|L1.212|
000014 492f LDR r1,|L1.212|
000016 1ac2 SUBS r2,r0,r3
000018 3980 SUBS r1,r1,#0x80
00001a 4298 CMP r0,r3
00001c d045 BEQ |L1.170|
00001e dc18 BGT |L1.82|
000020 4b2d LDR r3,|L1.216|
000022 eba0eba0 SUB r2,r0,r3
000026 4298 CMP r0,r3
000028 d037 BEQ |L1.154|
00002a dc0a BGT |L1.66|
00002c 4a2b LDR r2,|L1.220|
00002e 1880 ADDS r0,r0,r2
000030 d02b BEQ |L1.138|
000032 2814 CMP r0,#0x14
000034 d02d BEQ |L1.146|
000036 2828 CMP r0,#0x28
000038 d126 BNE |L1.136|
;;;84 {
;;;85 case DMA1_Channel1_BASE:
;;;86 /* Reset interrupt pending bits for DMA1 Channel1 */
;;;87 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
;;;88 break;
;;;89
;;;90 case DMA1_Channel2_BASE:
;;;91 /* Reset interrupt pending bits for DMA1 Channel2 */
;;;92 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
;;;93 break;
;;;94
;;;95 case DMA1_Channel3_BASE:
;;;96 /* Reset interrupt pending bits for DMA1 Channel3 */
;;;97 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
00003a 6848 LDR r0,[r1,#4]
00003c f440f440 ORR r0,r0,#0xf00
;;;98 break;
000040 e036 B |L1.176|
|L1.66|
000042 2a14 CMP r2,#0x14 ;83
000044 d02d BEQ |L1.162|
000046 2a28 CMP r2,#0x28 ;83
000048 d11e BNE |L1.136|
;;;99
;;;100 case DMA1_Channel4_BASE:
;;;101 /* Reset interrupt pending bits for DMA1 Channel4 */
;;;102 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
;;;103 break;
;;;104
;;;105 case DMA1_Channel5_BASE:
;;;106 /* Reset interrupt pending bits for DMA1 Channel5 */
;;;107 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
;;;108 break;
;;;109
;;;110 case DMA1_Channel6_BASE:
;;;111 /* Reset interrupt pending bits for DMA1 Channel6 */
;;;112 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
00004a 6848 LDR r0,[r1,#4]
00004c f440f440 ORR r0,r0,#0xf00000
;;;113 break;
000050 e02e B |L1.176|
|L1.82|
000052 f5b2f5b2 CMP r2,#0x3b0 ;83
000056 d032 BEQ |L1.190|
000058 dc0a BGT |L1.112|
00005a f5b2f5b2 CMP r2,#0x388 ;83
00005e d029 BEQ |L1.180|
000060 f5b2f5b2 CMP r2,#0x39c ;83
000064 d110 BNE |L1.136|
;;;114
;;;115 case DMA1_Channel7_BASE:
;;;116 /* Reset interrupt pending bits for DMA1 Channel7 */
;;;117 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
;;;118 break;
;;;119
;;;120 case DMA2_Channel1_BASE:
;;;121 /* Reset interrupt pending bits for DMA2 Channel1 */
;;;122 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
;;;123 break;
;;;124
;;;125 case DMA2_Channel2_BASE:
;;;126 /* Reset interrupt pending bits for DMA2 Channel2 */
;;;127 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
000066 f8d1f8d1 LDR r0,[r1,#0x404]
00006a f040f040 ORR r0,r0,#0xf0
;;;128 break;
00006e e009 B |L1.132|
|L1.112|
000070 f5b2f5b2 CMP r2,#0x3c4 ;83
000074 d028 BEQ |L1.200|
000076 f5b2f5b2 CMP r2,#0x3d8 ;83
00007a d105 BNE |L1.136|
;;;129
;;;130 case DMA2_Channel3_BASE:
;;;131 /* Reset interrupt pending bits for DMA2 Channel3 */
;;;132 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
;;;133 break;
;;;134
;;;135 case DMA2_Channel4_BASE:
;;;136 /* Reset interrupt pending bits for DMA2 Channel4 */
;;;137 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
;;;138 break;
;;;139
;;;140 case DMA2_Channel5_BASE:
;;;141 /* Reset interrupt pending bits for DMA2 Channel5 */
;;;142 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
00007c f8d1f8d1 LDR r0,[r1,#0x404]
000080 f440f440 ORR r0,r0,#0xf0000
|L1.132|
000084 f8c1f8c1 STR r0,[r1,#0x404]
|L1.136|
;;;143 break;
;;;144
;;;145 default:
;;;146 break;
;;;147 }
;;;148 }
000088 4770 BX lr
|L1.138|
00008a 6848 LDR r0,[r1,#4] ;87
00008c f040f040 ORR r0,r0,#0xf ;87
000090 e00e B |L1.176|
|L1.146|
000092 6848 LDR r0,[r1,#4] ;92
000094 f040f040 ORR r0,r0,#0xf0 ;92
000098 e00a B |L1.176|
|L1.154|
00009a 6848 LDR r0,[r1,#4] ;102
00009c f440f440 ORR r0,r0,#0xf000 ;102
0000a0 e006 B |L1.176|
|L1.162|
0000a2 6848 LDR r0,[r1,#4] ;107
0000a4 f440f440 ORR r0,r0,#0xf0000 ;107
0000a8 e002 B |L1.176|
|L1.170|
0000aa 6848 LDR r0,[r1,#4] ;117
0000ac f040f040 ORR r0,r0,#0xf000000 ;117
|L1.176|
0000b0 6048 STR r0,[r1,#4] ;117
0000b2 4770 BX lr
|L1.180|
0000b4 f8d1f8d1 LDR r0,[r1,#0x404] ;122
0000b8 f040f040 ORR r0,r0,#0xf ;122
0000bc e7e2 B |L1.132|
|L1.190|
0000be f8d1f8d1 LDR r0,[r1,#0x404] ;132
0000c2 f440f440 ORR r0,r0,#0xf00 ;132
0000c6 e7dd B |L1.132|
|L1.200|
0000c8 f8d1f8d1 LDR r0,[r1,#0x404] ;137
0000cc f440f440 ORR r0,r0,#0xf000 ;137
0000d0 e7d8 B |L1.132|
;;;149
ENDP
0000d2 0000 DCW 0x0000
|L1.212|
0000d4 40020080 DCD 0x40020080
|L1.216|
0000d8 40020044 DCD 0x40020044
|L1.220|
0000dc bffdfff8 DCD 0xbffdfff8
AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=1
DMA_Init PROC
;;;163 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
;;;164 {
000000 b570 PUSH {r4-r6,lr}
;;;165 u32 tmpreg = 0;
;;;166
;;;167 /* Check the parameters */
;;;168 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;169 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
;;;170 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;171 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;172 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
;;;173 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;174 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;175 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;176 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;177 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
;;;178
;;;179 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
;;;180 /* Get the DMAy_Channelx CCR value */
;;;181 tmpreg = DMAy_Channelx->CCR;
000002 6802 LDR r2,[r0,#0]
;;;182 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
;;;183 tmpreg &= CCR_CLEAR_Mask;
000004 f647f647 MOV r3,#0x7ff0
000008 439a BICS r2,r2,r3
;;;184 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
;;;185 /* Set DIR bit according to DMA_DIR value */
;;;186 /* Set CIRC bit according to DMA_Mode value */
;;;187 /* Set PINC bit according to DMA_PeripheralInc value */
;;;188 /* Set MINC bit according to DMA_MemoryInc value */
;;;189 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;190 /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;191 /* Set PL bits according to DMA_Priority value */
;;;192 /* Set the MEM2MEM bit according to DMA_M2M value */
;;;193 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00000a 6a0e LDR r6,[r1,#0x20]
00000c 688b LDR r3,[r1,#8]
00000e 690c LDR r4,[r1,#0x10]
000010 4333 ORRS r3,r3,r6
000012 e9d1e9d1 LDRD r5,r6,[r1,#0x14]
000016 432c ORRS r4,r4,r5
000018 4323 ORRS r3,r3,r4
00001a 69cc LDR r4,[r1,#0x1c]
00001c 4333 ORRS r3,r3,r6
00001e 4323 ORRS r3,r3,r4
000020 e9d1e9d1 LDRD r5,r4,[r1,#0x24]
000024 432b ORRS r3,r3,r5
000026 4323 ORRS r3,r3,r4
000028 4313 ORRS r3,r3,r2
;;;194 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;195 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
;;;196 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
;;;197 /* Write to DMAy Channelx CCR */
;;;198 DMAy_Channelx->CCR = tmpreg;
00002a 6003 STR r3,[r0,#0]
;;;199
;;;200 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
;;;201 /* Write to DMAy Channelx CNDTR */
;;;202 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00002c 68ca LDR r2,[r1,#0xc]
00002e 6042 STR r2,[r0,#4]
;;;203
;;;204 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
;;;205 /* Write to DMAy Channelx CPAR */
;;;206 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
000030 680a LDR r2,[r1,#0]
000032 6082 STR r2,[r0,#8]
;;;207
;;;208 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
;;;209 /* Write to DMAy Channelx CMAR */
;;;210 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
000034 6849 LDR r1,[r1,#4]
000036 60c1 STR r1,[r0,#0xc]
;;;211 }
000038 bd70 POP {r4-r6,pc}
;;;212
ENDP
AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1
DMA_StructInit PROC
;;;224 /* Initialize the DMA_PeripheralBaseAddr member */
;;;225 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
000000 2100 MOVS r1,#0
;;;226
;;;227 /* Initialize the DMA_MemoryBaseAddr member */
;;;228 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
000002 6001 STR r1,[r0,#0]
;;;229
;;;230 /* Initialize the DMA_DIR member */
;;;231 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
000004 6041 STR r1,[r0,#4]
;;;232
;;;233 /* Initialize the DMA_BufferSize member */
;;;234 DMA_InitStruct->DMA_BufferSize = 0;
000006 6081 STR r1,[r0,#8]
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