📄 stm32f10x_rcc.txt
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RCC_HCLKConfig PROC
;;;393
;;;394 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L11.16|
000002 6851 LDR r1,[r2,#4]
;;;395
;;;396 /* Clear HPRE[3:0] bits */
;;;397 tmpreg &= CFGR_HPRE_Reset_Mask;
000004 f021f021 BIC r1,r1,#0xf0
;;;398
;;;399 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;400 tmpreg |= RCC_SYSCLK;
000008 4301 ORRS r1,r1,r0
;;;401
;;;402 /* Store the new value */
;;;403 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;404 }
00000c 4770 BX lr
;;;405
ENDP
00000e 0000 DCW 0x0000
|L11.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_PCLK1Config||, CODE, READONLY, ALIGN=2
RCC_PCLK1Config PROC
;;;426
;;;427 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L12.16|
000002 6851 LDR r1,[r2,#4]
;;;428
;;;429 /* Clear PPRE1[2:0] bits */
;;;430 tmpreg &= CFGR_PPRE1_Reset_Mask;
000004 f421f421 BIC r1,r1,#0x700
;;;431
;;;432 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
;;;433 tmpreg |= RCC_HCLK;
000008 4301 ORRS r1,r1,r0
;;;434
;;;435 /* Store the new value */
;;;436 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;437 }
00000c 4770 BX lr
;;;438
ENDP
00000e 0000 DCW 0x0000
|L12.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_PCLK2Config||, CODE, READONLY, ALIGN=2
RCC_PCLK2Config PROC
;;;459
;;;460 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L13.16|
000002 6851 LDR r1,[r2,#4]
;;;461
;;;462 /* Clear PPRE2[2:0] bits */
;;;463 tmpreg &= CFGR_PPRE2_Reset_Mask;
000004 f421f421 BIC r1,r1,#0x3800
;;;464
;;;465 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
;;;466 tmpreg |= RCC_HCLK << 3;
000008 ea41ea41 ORR r0,r1,r0,LSL #3
;;;467
;;;468 /* Store the new value */
;;;469 RCC->CFGR = tmpreg;
00000c 6050 STR r0,[r2,#4]
;;;470 }
00000e 4770 BX lr
;;;471
ENDP
|L13.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2
RCC_ITConfig PROC
;;;488 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
;;;489 {
000000 4a04 LDR r2,|L14.20|
;;;490 /* Check the parameters */
;;;491 assert_param(IS_RCC_IT(RCC_IT));
;;;492 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;493
;;;494 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;495 {
;;;496 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;497 *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
000004 7a51 LDRB r1,[r2,#9]
000006 d001 BEQ |L14.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L14.14|
|L14.12|
;;;498 }
;;;499 else
;;;500 {
;;;501 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;502 *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
00000c 4381 BICS r1,r1,r0
|L14.14|
00000e 7251 STRB r1,[r2,#9] ;497
;;;503 }
;;;504 }
000010 4770 BX lr
;;;505
ENDP
000012 0000 DCW 0x0000
|L14.20|
000014 40021000 DCD 0x40021000
AREA ||i.RCC_USBCLKConfig||, CODE, READONLY, ALIGN=2
RCC_USBCLKConfig PROC
;;;519 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
;;;520 {
000000 4901 LDR r1,|L15.8|
;;;521 /* Check the parameters */
;;;522 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
;;;523
;;;524 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
000002 6008 STR r0,[r1,#0]
;;;525 }
000004 4770 BX lr
;;;526
ENDP
000006 0000 DCW 0x0000
|L15.8|
000008 424200d8 DCD 0x424200d8
AREA ||i.RCC_ADCCLKConfig||, CODE, READONLY, ALIGN=2
RCC_ADCCLKConfig PROC
;;;546
;;;547 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L16.16|
000002 6851 LDR r1,[r2,#4]
;;;548
;;;549 /* Clear ADCPRE[1:0] bits */
;;;550 tmpreg &= CFGR_ADCPRE_Reset_Mask;
000004 f421f421 BIC r1,r1,#0xc000
;;;551
;;;552 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
;;;553 tmpreg |= RCC_PCLK2;
000008 4301 ORRS r1,r1,r0
;;;554
;;;555 /* Store the new value */
;;;556 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;557 }
00000c 4770 BX lr
;;;558
ENDP
00000e 0000 DCW 0x0000
|L16.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2
RCC_LSEConfig PROC
;;;577 /* Reset LSEON bit */
;;;578 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
000000 4906 LDR r1,|L17.28|
000002 2200 MOVS r2,#0
000004 700a STRB r2,[r1,#0]
;;;579
;;;580 /* Reset LSEBYP bit */
;;;581 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
000006 f801f801 STRB r2,[r1],#-0x20
;;;582
;;;583 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;584 switch(RCC_LSE)
00000a 2801 CMP r0,#1
00000c d002 BEQ |L17.20|
00000e 2804 CMP r0,#4
000010 d102 BNE |L17.24|
;;;585 {
;;;586 case RCC_LSE_ON:
;;;587 /* Set LSEON bit */
;;;588 *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
;;;589 break;
;;;590
;;;591 case RCC_LSE_Bypass:
;;;592 /* Set LSEBYP and LSEON bits */
;;;593 *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
000012 2005 MOVS r0,#5
|L17.20|
000014 f881f881 STRB r0,[r1,#0x20]
|L17.24|
;;;594 break;
;;;595
;;;596 default:
;;;597 break;
;;;598 }
;;;599 }
000018 4770 BX lr
;;;600
ENDP
00001a 0000 DCW 0x0000
|L17.28|
00001c 40021020 DCD 0x40021020
AREA ||i.RCC_LSICmd||, CODE, READONLY, ALIGN=2
RCC_LSICmd PROC
;;;610 void RCC_LSICmd(FunctionalState NewState)
;;;611 {
000000 4901 LDR r1,|L18.8|
;;;612 /* Check the parameters */
;;;613 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;614
;;;615 *(vu32 *) CSR_LSION_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;616 }
000004 4770 BX lr
;;;617
ENDP
000006 0000 DCW 0x0000
|L18.8|
000008 42420480 DCD 0x42420480
AREA ||i.RCC_RTCCLKConfig||, CODE, READONLY, ALIGN=2
RCC_RTCCLKConfig PROC
;;;637 /* Select the RTC clock source */
;;;638 RCC->BDCR |= RCC_RTCCLKSource;
000000 4902 LDR r1,|L19.12|
000002 6a0a LDR r2,[r1,#0x20]
000004 4302 ORRS r2,r2,r0
000006 620a STR r2,[r1,#0x20]
;;;639 }
000008 4770 BX lr
;;;640
ENDP
00000a 0000 DCW 0x0000
|L19.12|
00000c 40021000 DCD 0x40021000
AREA ||i.RCC_RTCCLKCmd||, CODE, READONLY, ALIGN=2
RCC_RTCCLKCmd PROC
;;;651 void RCC_RTCCLKCmd(FunctionalState NewState)
;;;652 {
000000 4901 LDR r1,|L20.8|
;;;653 /* Check the parameters */
;;;654 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;655
;;;656 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;657 }
000004 4770 BX lr
;;;658
ENDP
000006 0000 DCW 0x0000
|L20.8|
000008 4242043c DCD 0x4242043c
AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2
RCC_GetClocksFreq PROC
;;;667 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
;;;668 {
000000 b530 PUSH {r4,r5,lr}
;;;669 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
;;;670
;;;671 /* Get SYSCLK source -------------------------------------------------------*/
;;;672 tmp = RCC->CFGR & CFGR_SWS_Mask;
000002 4a20 LDR r2,|L21.132|
000004 6851 LDR r1,[r2,#4]
000006 4b20 LDR r3,|L21.136|
000008 f011f011 ANDS r1,r1,#0xc
;;;673
;;;674 switch (tmp)
00000c d003 BEQ |L21.22|
00000e 2904 CMP r1,#4
000010 d001 BEQ |L21.22|
000012 2908 CMP r1,#8
000014 d001 BEQ |L21.26|
|L21.22|
;;;675 {
;;;676 case 0x00: /* HSI used as system clock */
;;;677 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;678 break;
000016 6003 STR r3,[r0,#0]
000018 e011 B |L21.62|
|L21.26|
;;;679
;;;680 case 0x04: /* HSE used as system clock */
;;;681 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
;;;682 break;
;;;683
;;;684 case 0x08: /* PLL used as system clock */
;;;685 /* Get PLL clock source and multiplication factor ----------------------*/
;;;686 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00001a 6851 LDR r1,[r2,#4]
;;;687 pllmull = ( pllmull >> 18) + 2;
00001c 2402 MOVS r4,#2
00001e f401f401 AND r1,r1,#0x3c0000 ;686
000022 eb04eb04 ADD r1,r4,r1,LSR #18
;;;688
;;;689 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000026 6854 LDR r4,[r2,#4]
000028 4d18 LDR r5,|L21.140|
00002a f414f414 TST r4,#0x10000
;;;690
;;;691 if (pllsource == 0x00)
00002e d002 BEQ |L21.54|
;;;692 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;693 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
;;;694 }
;;;695 else
;;;696 {/* HSE selected as PLL clock entry */
;;;697
;;;698 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
000030 6854 LDR r4,[r2,#4]
000032 03a4 LSLS r4,r4,#14
000034 d501 BPL |L21.58|
|L21.54|
000036 4369 MULS r1,r5,r1 ;693
000038 e000 B |L21.60|
|L21.58|
;;;699 {/* HSE oscillator clock divided by 2 */
;;;700
;;;701 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
;;;702 }
;;;703 else
;;;704 {
;;;705 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
00003a 4359 MULS r1,r3,r1
|L21.60|
00003c 6001 STR r1,[r0,#0] ;701
|L21.62|
;;;706 }
;;;707 }
;;;708 break;
;;;709
;;;710 default:
;;;711 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;712 break;
;;;713 }
;;;714
;;;715 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;716 /* Get HCLK prescaler */
;;;717 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00003e 6851 LDR r1,[r2,#4]
;;;718 tmp = tmp >> 4;
;;;719 presc = APBAHBPrescTable[tmp];
000040 4b13 LDR r3,|L21.144|
000042 f001f001 AND r1,r1,#0xf0 ;717
000046 0909 LSRS r1,r1,#4 ;718
000048 5c5c LDRB r4,[r3,r1]
;;;720
;;;721 /* HCLK clock frequency */
;;;722 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00004a 6801 LDR r1,[r0,#0]
00004c 40e1 LSRS r1,r1,r4
;;;723
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