📄 stm32f10x_rcc.txt
字号:
; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_rcc.o --depend=.\Obj\stm32f10x_rcc.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_rcc.crf ..\..\..\FWLib\library\src\stm32f10x_rcc.c]
THUMB
AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;127 /* Set HSION bit */
;;;128 RCC->CR |= (u32)0x00000001;
000000 480b LDR r0,|L1.48|
000002 6801 LDR r1,[r0,#0]
000004 f041f041 ORR r1,r1,#1
000008 6001 STR r1,[r0,#0]
;;;129
;;;130 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
;;;131 RCC->CFGR &= (u32)0xF8FF0000;
00000a 6841 LDR r1,[r0,#4]
00000c 4a09 LDR r2,|L1.52|
00000e 4011 ANDS r1,r1,r2
000010 6041 STR r1,[r0,#4]
;;;132
;;;133 /* Reset HSEON, CSSON and PLLON bits */
;;;134 RCC->CR &= (u32)0xFEF6FFFF;
000012 6801 LDR r1,[r0,#0]
000014 4a08 LDR r2,|L1.56|
000016 4011 ANDS r1,r1,r2
000018 6001 STR r1,[r0,#0]
;;;135
;;;136 /* Reset HSEBYP bit */
;;;137 RCC->CR &= (u32)0xFFFBFFFF;
00001a 6801 LDR r1,[r0,#0]
00001c f421f421 BIC r1,r1,#0x40000
000020 6001 STR r1,[r0,#0]
;;;138
;;;139 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;140 RCC->CFGR &= (u32)0xFF80FFFF;
000022 6842 LDR r2,[r0,#4]
;;;141
;;;142 /* Disable all interrupts */
;;;143 RCC->CIR = 0x00000000;
000024 2100 MOVS r1,#0
000026 f422f422 BIC r2,r2,#0x7f0000 ;140
00002a 6042 STR r2,[r0,#4] ;140
00002c 6081 STR r1,[r0,#8]
;;;144 }
00002e 4770 BX lr
;;;145
ENDP
|L1.48|
000030 40021000 DCD 0x40021000
|L1.52|
000034 f8ff0000 DCD 0xf8ff0000
|L1.56|
000038 fef6ffff DCD 0xfef6ffff
AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2
RCC_HSEConfig PROC
;;;166 /* Reset HSEON bit */
;;;167 RCC->CR &= CR_HSEON_Reset;
000000 490b LDR r1,|L2.48|
000002 680a LDR r2,[r1,#0]
000004 f422f422 BIC r2,r2,#0x10000
000008 600a STR r2,[r1,#0]
;;;168
;;;169 /* Reset HSEBYP bit */
;;;170 RCC->CR &= CR_HSEBYP_Reset;
00000a 680a LDR r2,[r1,#0]
;;;171
;;;172 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;173 switch(RCC_HSE)
00000c f5b0f5b0 CMP r0,#0x10000
000010 f422f422 BIC r2,r2,#0x40000 ;170
000014 600a STR r2,[r1,#0] ;170
000016 d007 BEQ |L2.40|
000018 f5b0f5b0 CMP r0,#0x40000
00001c d103 BNE |L2.38|
;;;174 {
;;;175 case RCC_HSE_ON:
;;;176 /* Set HSEON bit */
;;;177 RCC->CR |= CR_HSEON_Set;
;;;178 break;
;;;179
;;;180 case RCC_HSE_Bypass:
;;;181 /* Set HSEBYP and HSEON bits */
;;;182 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00001e 6808 LDR r0,[r1,#0]
000020 f440f440 ORR r0,r0,#0x50000
|L2.36|
000024 6008 STR r0,[r1,#0]
|L2.38|
;;;183 break;
;;;184
;;;185 default:
;;;186 break;
;;;187 }
;;;188 }
000026 4770 BX lr
|L2.40|
000028 6808 LDR r0,[r1,#0] ;177
00002a f440f440 ORR r0,r0,#0x10000 ;177
00002e e7f9 B |L2.36|
;;;189
ENDP
|L2.48|
000030 40021000 DCD 0x40021000
AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2
RCC_GetFlagStatus PROC
;;;988 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
;;;989 {
000000 4603 MOV r3,r0
;;;990 u32 tmp = 0;
;;;991 u32 statusreg = 0;
;;;992 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;993
;;;994 /* Check the parameters */
;;;995 assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;996
;;;997 /* Get the RCC register index */
;;;998 tmp = RCC_FLAG >> 5;
000004 0959 LSRS r1,r3,#5
000006 4a09 LDR r2,|L3.44|
;;;999
;;;1000 if (tmp == 1) /* The flag to check is in CR register */
000008 2901 CMP r1,#1
00000a d101 BNE |L3.16|
;;;1001 {
;;;1002 statusreg = RCC->CR;
00000c 6811 LDR r1,[r2,#0]
00000e e004 B |L3.26|
|L3.16|
;;;1003 }
;;;1004 else if (tmp == 2) /* The flag to check is in BDCR register */
000010 2902 CMP r1,#2
000012 d101 BNE |L3.24|
;;;1005 {
;;;1006 statusreg = RCC->BDCR;
000014 6a11 LDR r1,[r2,#0x20]
000016 e000 B |L3.26|
|L3.24|
;;;1007 }
;;;1008 else /* The flag to check is in CSR register */
;;;1009 {
;;;1010 statusreg = RCC->CSR;
000018 6a51 LDR r1,[r2,#0x24]
|L3.26|
;;;1011 }
;;;1012
;;;1013 /* Get the flag position */
;;;1014 tmp = RCC_FLAG & FLAG_Mask;
00001a f003f003 AND r2,r3,#0x1f
;;;1015
;;;1016 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
00001e 2301 MOVS r3,#1
000020 4093 LSLS r3,r3,r2
000022 420b TST r3,r1
000024 d000 BEQ |L3.40|
;;;1017 {
;;;1018 bitstatus = SET;
000026 2001 MOVS r0,#1
|L3.40|
;;;1019 }
;;;1020 else
;;;1021 {
;;;1022 bitstatus = RESET;
;;;1023 }
;;;1024
;;;1025 /* Return the flag status */
;;;1026 return bitstatus;
;;;1027 }
000028 4770 BX lr
;;;1028
ENDP
00002a 0000 DCW 0x0000
|L3.44|
00002c 40021000 DCD 0x40021000
AREA ||i.RCC_WaitForHSEStartUp||, CODE, READONLY, ALIGN=2
RCC_WaitForHSEStartUp PROC
;;;199 ErrorStatus RCC_WaitForHSEStartUp(void)
;;;200 {
000000 b530 PUSH {r4,r5,lr}
000002 4c0b LDR r4,|L4.48|
000004 f240f240 MOV r5,#0x1ff
|L4.8|
;;;201 ErrorStatus status = ERROR;
;;;202
;;;203 /* Wait till HSE is ready and if Time out is reached exit */
;;;204 do
;;;205 {
;;;206 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
000008 2031 MOVS r0,#0x31
00000a f7fff7ff BL RCC_GetFlagStatus
00000e 7020 STRB r0,[r4,#0] ; HSEStatus
;;;207 StartUpCounter++;
000010 6860 LDR r0,[r4,#4] ; StartUpCounter
000012 1c40 ADDS r0,r0,#1
000014 6060 STR r0,[r4,#4] ; StartUpCounter
;;;208 } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
000016 7820 LDRB r0,[r4,#0] ; HSEStatus
000018 b910 CBNZ r0,|L4.32|
00001a 6860 LDR r0,[r4,#4] ; StartUpCounter
00001c 42a8 CMP r0,r5
00001e d1f3 BNE |L4.8|
|L4.32|
;;;209
;;;210
;;;211 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
000020 2031 MOVS r0,#0x31
000022 f7fff7ff BL RCC_GetFlagStatus
000026 2800 CMP r0,#0
000028 d000 BEQ |L4.44|
;;;212 {
;;;213 status = SUCCESS;
00002a 2001 MOVS r0,#1
|L4.44|
;;;214 }
;;;215 else
;;;216 {
;;;217 status = ERROR;
;;;218 }
;;;219
;;;220 return (status);
;;;221 }
00002c bd30 POP {r4,r5,pc}
;;;222
ENDP
00002e 0000 DCW 0x0000
|L4.48|
000030 00000000 DCD ||.data||
AREA ||i.RCC_AdjustHSICalibrationValue||, CODE, READONLY, ALIGN=2
RCC_AdjustHSICalibrationValue PROC
;;;238
;;;239 tmpreg = RCC->CR;
000000 4a03 LDR r2,|L5.16|
000002 6811 LDR r1,[r2,#0]
;;;240
;;;241 /* Clear HSITRIM[4:0] bits */
;;;242 tmpreg &= CR_HSITRIM_Mask;
000004 f021f021 BIC r1,r1,#0xf8
;;;243
;;;244 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;245 tmpreg |= (u32)HSICalibrationValue << 3;
000008 ea41ea41 ORR r0,r1,r0,LSL #3
;;;246
;;;247 /* Store the new value */
;;;248 RCC->CR = tmpreg;
00000c 6010 STR r0,[r2,#0]
;;;249 }
00000e 4770 BX lr
;;;250
ENDP
|L5.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2
RCC_HSICmd PROC
;;;265
;;;266 *(vu32 *) CR_HSION_BB = (u32)NewState;
000000 4901 LDR r1,|L6.8|
000002 6008 STR r0,[r1,#0]
;;;267 }
000004 4770 BX lr
;;;268
ENDP
000006 0000 DCW 0x0000
|L6.8|
000008 42420000 DCD 0x42420000
AREA ||i.RCC_PLLConfig||, CODE, READONLY, ALIGN=2
RCC_PLLConfig PROC
;;;293
;;;294 tmpreg = RCC->CFGR;
000000 4b03 LDR r3,|L7.16|
000002 685a LDR r2,[r3,#4]
;;;295
;;;296 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
;;;297 tmpreg &= CFGR_PLL_Mask;
;;;298
;;;299 /* Set the PLL configuration bits */
;;;300 tmpreg |= RCC_PLLSource | RCC_PLLMul;
000004 4308 ORRS r0,r0,r1
000006 f422f422 BIC r2,r2,#0x3f0000 ;297
00000a 4310 ORRS r0,r0,r2
;;;301
;;;302 /* Store the new value */
;;;303 RCC->CFGR = tmpreg;
00000c 6058 STR r0,[r3,#4]
;;;304 }
00000e 4770 BX lr
;;;305
ENDP
|L7.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_PLLCmd||, CODE, READONLY, ALIGN=2
RCC_PLLCmd PROC
;;;319
;;;320 *(vu32 *) CR_PLLON_BB = (u32)NewState;
000000 4901 LDR r1,|L8.8|
000002 6608 STR r0,[r1,#0x60]
;;;321 }
000004 4770 BX lr
;;;322
ENDP
000006 0000 DCW 0x0000
|L8.8|
000008 42420000 DCD 0x42420000
AREA ||i.RCC_SYSCLKConfig||, CODE, READONLY, ALIGN=2
RCC_SYSCLKConfig PROC
;;;340
;;;341 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L9.16|
000002 6851 LDR r1,[r2,#4]
;;;342
;;;343 /* Clear SW[1:0] bits */
;;;344 tmpreg &= CFGR_SW_Mask;
000004 f021f021 BIC r1,r1,#3
;;;345
;;;346 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;347 tmpreg |= RCC_SYSCLKSource;
000008 4301 ORRS r1,r1,r0
;;;348
;;;349 /* Store the new value */
;;;350 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;351 }
00000c 4770 BX lr
;;;352
ENDP
00000e 0000 DCW 0x0000
|L9.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2
RCC_GetSYSCLKSource PROC
;;;365 {
;;;366 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
000000 4802 LDR r0,|L10.12|
000002 6840 LDR r0,[r0,#4]
000004 f000f000 AND r0,r0,#0xc
;;;367 }
000008 4770 BX lr
;;;368
ENDP
00000a 0000 DCW 0x0000
|L10.12|
00000c 40021000 DCD 0x40021000
AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -