📄 stm32f10x_spi.txt
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AREA ||i.SPI_TransmitCRC||, CODE, READONLY, ALIGN=1
SPI_TransmitCRC PROC
;;;587 /* Enable the selected SPI CRC transmission */
;;;588 SPIx->CR1 |= CR1_CRCNext_Set;
000000 8801 LDRH r1,[r0,#0]
000002 f441f441 ORR r1,r1,#0x1000
000006 8001 STRH r1,[r0,#0]
;;;589 }
000008 4770 BX lr
;;;590
ENDP
AREA ||i.SPI_CalculateCRC||, CODE, READONLY, ALIGN=1
SPI_CalculateCRC PROC
;;;606
;;;607 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;608 {
;;;609 /* Enable the selected SPI CRC calculation */
;;;610 SPIx->CR1 |= CR1_CRCEN_Set;
000002 8801 LDRH r1,[r0,#0]
000004 d002 BEQ |L16.12|
000006 f441f441 ORR r1,r1,#0x2000
00000a e001 B |L16.16|
|L16.12|
;;;611 }
;;;612 else
;;;613 {
;;;614 /* Disable the selected SPI CRC calculation */
;;;615 SPIx->CR1 &= CR1_CRCEN_Reset;
00000c f421f421 BIC r1,r1,#0x2000
|L16.16|
000010 8001 STRH r1,[r0,#0] ;610
;;;616 }
;;;617 }
000012 4770 BX lr
;;;618
ENDP
AREA ||i.SPI_GetCRC||, CODE, READONLY, ALIGN=1
SPI_GetCRC PROC
;;;638
;;;639 if (SPI_CRC != SPI_CRC_Rx)
000000 2901 CMP r1,#1
000002 d001 BEQ |L17.8|
;;;640 {
;;;641 /* Get the Tx CRC register */
;;;642 crcreg = SPIx->TXCRCR;
000004 8b00 LDRH r0,[r0,#0x18]
;;;643 }
;;;644 else
;;;645 {
;;;646 /* Get the Rx CRC register */
;;;647 crcreg = SPIx->RXCRCR;
;;;648 }
;;;649
;;;650 /* Return the selected CRC register */
;;;651 return crcreg;
;;;652 }
000006 4770 BX lr
|L17.8|
000008 8a80 LDRH r0,[r0,#0x14] ;647
00000a 4770 BX lr
;;;653
ENDP
AREA ||i.SPI_GetCRCPolynomial||, CODE, READONLY, ALIGN=1
SPI_GetCRCPolynomial PROC
;;;666 /* Return the CRC polynomial register */
;;;667 return SPIx->CRCPR;
000000 8a00 LDRH r0,[r0,#0x10]
;;;668 }
000002 4770 BX lr
;;;669
ENDP
AREA ||i.SPI_BiDirectionalLineConfig||, CODE, READONLY, ALIGN=1
SPI_BiDirectionalLineConfig PROC
;;;688
;;;689 if (SPI_Direction == SPI_Direction_Tx)
000000 f5b1f5b1 CMP r1,#0x4000
;;;690 {
;;;691 /* Set the Tx only mode */
;;;692 SPIx->CR1 |= SPI_Direction_Tx;
000004 8801 LDRH r1,[r0,#0]
000006 d102 BNE |L19.14|
000008 f441f441 ORR r1,r1,#0x4000
00000c e001 B |L19.18|
|L19.14|
;;;693 }
;;;694 else
;;;695 {
;;;696 /* Set the Rx only mode */
;;;697 SPIx->CR1 &= SPI_Direction_Rx;
00000e f421f421 BIC r1,r1,#0x4000
|L19.18|
000012 8001 STRH r1,[r0,#0] ;692
;;;698 }
;;;699 }
000014 4770 BX lr
;;;700
ENDP
AREA ||i.SPI_I2S_GetFlagStatus||, CODE, READONLY, ALIGN=1
SPI_I2S_GetFlagStatus PROC
;;;720 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)
;;;721 {
000000 4602 MOV r2,r0
;;;722 FlagStatus bitstatus = RESET;
;;;723
;;;724 /* Check the parameters */
;;;725 assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;726 assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
;;;727
;;;728 /* Check the status of the specified SPI/I2S flag */
;;;729 if ((SPIx->SR & SPI_I2S_FLAG) != (u16)RESET)
000002 8912 LDRH r2,[r2,#8]
000004 2000 MOVS r0,#0 ;722
000006 420a TST r2,r1
000008 d000 BEQ |L20.12|
;;;730 {
;;;731 /* SPI_I2S_FLAG is set */
;;;732 bitstatus = SET;
00000a 2001 MOVS r0,#1
|L20.12|
;;;733 }
;;;734 else
;;;735 {
;;;736 /* SPI_I2S_FLAG is reset */
;;;737 bitstatus = RESET;
;;;738 }
;;;739 /* Return the SPI_I2S_FLAG status */
;;;740 return bitstatus;
;;;741 }
00000c 4770 BX lr
;;;742
ENDP
AREA ||i.SPI_I2S_ClearFlag||, CODE, READONLY, ALIGN=1
SPI_I2S_ClearFlag PROC
;;;766 /* SPI_FLAG_MODF flag clear */
;;;767 if(SPI_I2S_FLAG == SPI_FLAG_MODF)
000000 2920 CMP r1,#0x20
000002 d105 BNE |L21.16|
;;;768 {
;;;769 /* Read SR register */
;;;770 (void)SPIx->SR;
000004 8901 LDRH r1,[r0,#8]
;;;771
;;;772 /* Write on CR1 register */
;;;773 SPIx->CR1 |= CR1_SPE_Set;
000006 8801 LDRH r1,[r0,#0]
000008 f041f041 ORR r1,r1,#0x40
00000c 8001 STRH r1,[r0,#0]
;;;774 }
;;;775 /* SPI_I2S_FLAG_OVR flag or I2S_FLAG_UDR flag clear */
;;;776 else if ((SPI_I2S_FLAG == SPI_I2S_FLAG_OVR) || (SPI_I2S_FLAG == I2S_FLAG_UDR))
;;;777 {
;;;778 /* Read SR register (Before clearing OVR flag, it is mandatory to read
;;;779 SPI_I2S_DR register)*/
;;;780 (void)SPIx->SR;
;;;781 }
;;;782 else /* SPI_FLAG_CRCERR flag clear */
;;;783 {
;;;784 /* Clear the selected SPI flag */
;;;785 SPIx->SR = (u16)~SPI_I2S_FLAG;
;;;786 }
;;;787 }
00000e 4770 BX lr
|L21.16|
000010 2940 CMP r1,#0x40 ;776
000012 d001 BEQ |L21.24|
000014 2908 CMP r1,#8 ;776
000016 d101 BNE |L21.28|
|L21.24|
000018 8900 LDRH r0,[r0,#8] ;780
00001a 4770 BX lr
|L21.28|
00001c 43c9 MVNS r1,r1 ;785
00001e 8101 STRH r1,[r0,#8] ;785
000020 4770 BX lr
;;;788
ENDP
AREA ||i.SPI_I2S_GetITStatus||, CODE, READONLY, ALIGN=1
SPI_I2S_GetITStatus PROC
;;;806 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)
;;;807 {
000000 b530 PUSH {r4,r5,lr}
;;;808 ITStatus bitstatus = RESET;
;;;809 u16 itpos = 0, itmask = 0, enablestatus = 0;
;;;810
;;;811 /* Check the parameters */
;;;812 assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;813 assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
;;;814
;;;815 /* Get the SPI/I2S IT index */
;;;816 itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
000002 f001f001 AND r5,r1,#0xf
000006 2401 MOVS r4,#1
000008 4602 MOV r2,r0 ;807
00000a fa04fa04 LSL r3,r4,r5
00000e 2000 MOVS r0,#0 ;808
;;;817
;;;818 /* Get the SPI/I2S IT mask */
;;;819 itmask = SPI_I2S_IT >> 4;
000010 0909 LSRS r1,r1,#4
;;;820 /* Set the IT mask */
;;;821 itmask = (u16)((u16)0x01 << itmask);
000012 408c LSLS r4,r4,r1
000014 b2a1 UXTH r1,r4
;;;822 /* Get the SPI_I2S_IT enable bit status */
;;;823 enablestatus = (SPIx->CR2 & itmask) ;
000016 8894 LDRH r4,[r2,#4]
000018 b29b UXTH r3,r3 ;816
;;;824
;;;825 /* Check the status of the specified SPI/I2S interrupt */
;;;826 if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)
00001a 8912 LDRH r2,[r2,#8]
00001c ea04ea04 AND r4,r4,r1 ;823
000020 421a TST r2,r3
000022 d002 BEQ |L22.42|
000024 2c00 CMP r4,#0
000026 d000 BEQ |L22.42|
;;;827 {
;;;828 /* SPI_I2S_IT is set */
;;;829 bitstatus = SET;
000028 2001 MOVS r0,#1
|L22.42|
;;;830 }
;;;831 else
;;;832 {
;;;833 /* SPI_I2S_IT is reset */
;;;834 bitstatus = RESET;
;;;835 }
;;;836 /* Return the SPI_I2S_IT status */
;;;837 return bitstatus;
;;;838 }
00002a bd30 POP {r4,r5,pc}
;;;839
ENDP
AREA ||i.SPI_I2S_ClearITPendingBit||, CODE, READONLY, ALIGN=1
SPI_I2S_ClearITPendingBit PROC
;;;863 /* SPI_IT_MODF pending bit clear */
;;;864 if(SPI_I2S_IT == SPI_IT_MODF)
000000 2955 CMP r1,#0x55
000002 d105 BNE |L23.16|
;;;865 {
;;;866 /* Read SR register */
;;;867 (void)SPIx->SR;
000004 8901 LDRH r1,[r0,#8]
;;;868 /* Write on CR1 register */
;;;869 SPIx->CR1 |= CR1_SPE_Set;
000006 8801 LDRH r1,[r0,#0]
000008 f041f041 ORR r1,r1,#0x40
00000c 8001 STRH r1,[r0,#0]
;;;870 }
;;;871 /* SPI_I2S_IT_OVR or I2S_IT_UDR pending bit clear */
;;;872 else if((SPI_I2S_IT == SPI_I2S_IT_OVR) || (SPI_I2S_IT == I2S_IT_UDR))
;;;873 {
;;;874 /* Read SR register */
;;;875 (void)(SPIx->SR);
;;;876 }
;;;877 else /* SPI_IT_CRCERR pending bit clear */
;;;878 {
;;;879 /* Get the SPI/I2S IT index */
;;;880 itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
;;;881 /* Clear the selected SPI/I2S interrupt pending bits */
;;;882 SPIx->SR = (u16)~itpos;
;;;883 }
;;;884 }
00000e 4770 BX lr
|L23.16|
000010 2956 CMP r1,#0x56 ;872
000012 d001 BEQ |L23.24|
000014 2953 CMP r1,#0x53 ;872
000016 d101 BNE |L23.28|
|L23.24|
000018 8900 LDRH r0,[r0,#8] ;875
00001a 4770 BX lr
|L23.28|
00001c f001f001 AND r2,r1,#0xf ;880
000020 2101 MOVS r1,#1 ;880
000022 4091 LSLS r1,r1,r2 ;880
000024 43c9 MVNS r1,r1 ;882
000026 8101 STRH r1,[r0,#8] ;882
000028 4770 BX lr
;;;885
ENDP
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