stm32f10x_spi.txt

STM32外部SRAM用作datamemery的程序 开发环境MDK

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_spi.o --depend=.\Obj\stm32f10x_spi.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_spi.crf ..\..\..\FWLib\library\src\stm32f10x_spi.c]
                          THUMB

                          AREA ||i.SPI_I2S_DeInit||, CODE, READONLY, ALIGN=2

                  SPI_I2S_DeInit PROC
;;;66       
;;;67       switch (*(u32*)&SPIx)
000000  4911              LDR      r1,|L1.72|
000002  b510              PUSH     {r4,lr}
000004  1840              ADDS     r0,r0,r1
000006  d010              BEQ      |L1.42|
000008  f5b0f5b0          CMP      r0,#0x400
00000c  d010              BEQ      |L1.48|
00000e  f5b0f5b0          CMP      r0,#0xf800
000012  d118              BNE      |L1.70|
;;;68       {
;;;69         case SPI1_BASE:
;;;70           /* Enable SPI1 reset state */
;;;71           RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
000014  2101              MOVS     r1,#1
000016  030c              LSLS     r4,r1,#12
000018  4620              MOV      r0,r4
00001a  f7fff7ff          BL       RCC_APB2PeriphResetCmd
;;;72           /* Release SPI1 from reset state */
;;;73           RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
00001e  4620              MOV      r0,r4
000020  e8bde8bd          POP      {r4,lr}
000024  2100              MOVS     r1,#0
000026  f7fff7ff          B.W      RCC_APB2PeriphResetCmd
                  |L1.42|
;;;74           break;
;;;75     
;;;76         case SPI2_BASE:
;;;77           /* Enable SPI2 reset state */
;;;78           RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
00002a  2101              MOVS     r1,#1
00002c  038c              LSLS     r4,r1,#14
;;;79           /* Release SPI2 from reset state */
;;;80           RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
;;;81           break;
00002e  e001              B        |L1.52|
                  |L1.48|
;;;82     
;;;83         case SPI3_BASE:
;;;84           /* Enable SPI3 reset state */
;;;85           RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
000030  2101              MOVS     r1,#1
000032  03cc              LSLS     r4,r1,#15
                  |L1.52|
000034  4620              MOV      r0,r4
000036  f7fff7ff          BL       RCC_APB1PeriphResetCmd
;;;86           /* Release SPI3 from reset state */
;;;87           RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
00003a  4620              MOV      r0,r4
00003c  e8bde8bd          POP      {r4,lr}
000040  2100              MOVS     r1,#0
000042  f7fff7ff          B.W      RCC_APB1PeriphResetCmd
                  |L1.70|
;;;88           break;
;;;89     
;;;90         default:
;;;91           break;
;;;92       }
;;;93     }
000046  bd10              POP      {r4,pc}
;;;94     
                          ENDP

                  |L1.72|
000048  bfffc800          DCD      0xbfffc800

                          AREA ||i.SPI_Init||, CODE, READONLY, ALIGN=1

                  SPI_Init PROC
;;;106    void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
;;;107    {
000000  b570              PUSH     {r4-r6,lr}
;;;108      u16 tmpreg = 0;
;;;109      
;;;110      /* check the parameters */
;;;111      assert_param(IS_SPI_ALL_PERIPH(SPIx));   
;;;112      
;;;113      /* Check the SPI parameters */
;;;114      assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
;;;115      assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
;;;116      assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
;;;117      assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
;;;118      assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
;;;119      assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
;;;120      assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
;;;121      assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
;;;122      assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
;;;123    
;;;124    /*---------------------------- SPIx CR1 Configuration ------------------------*/
;;;125      /* Get the SPIx CR1 value */
;;;126      tmpreg = SPIx->CR1;
000002  8802              LDRH     r2,[r0,#0]
;;;127      /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
;;;128      tmpreg &= CR1_CLEAR_Mask;
;;;129      /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
;;;130         master/salve mode, CPOL and CPHA */
;;;131      /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
;;;132      /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
;;;133      /* Set LSBFirst bit according to SPI_FirstBit value */
;;;134      /* Set BR bits according to SPI_BaudRatePrescaler value */
;;;135      /* Set CPOL bit according to SPI_CPOL value */
;;;136      /* Set CPHA bit according to SPI_CPHA value */
;;;137      tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
000004  880b              LDRH     r3,[r1,#0]
000006  884e              LDRH     r6,[r1,#2]
000008  888c              LDRH     r4,[r1,#4]
00000a  88cd              LDRH     r5,[r1,#6]
00000c  4333              ORRS     r3,r3,r6
00000e  432c              ORRS     r4,r4,r5
000010  890e              LDRH     r6,[r1,#8]
000012  4323              ORRS     r3,r3,r4
000014  894c              LDRH     r4,[r1,#0xa]
000016  4333              ORRS     r3,r3,r6
000018  898d              LDRH     r5,[r1,#0xc]
00001a  4323              ORRS     r3,r3,r4
00001c  89cc              LDRH     r4,[r1,#0xe]
00001e  432b              ORRS     r3,r3,r5
000020  f402f402          AND      r2,r2,#0x3040         ;128
000024  4323              ORRS     r3,r3,r4
000026  4313              ORRS     r3,r3,r2
;;;138                      SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
;;;139                      SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
;;;140                      SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
;;;141      /* Write to SPIx CR1 */
;;;142      SPIx->CR1 = tmpreg;
000028  8003              STRH     r3,[r0,#0]
;;;143      
;;;144      /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
;;;145      SPIx->I2SCFGR &= SPI_Mode_Select;		
00002a  8b82              LDRH     r2,[r0,#0x1c]
00002c  f422f422          BIC      r2,r2,#0x800
000030  8382              STRH     r2,[r0,#0x1c]
;;;146    
;;;147    /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
;;;148      /* Write to SPIx CRCPOLY */
;;;149      SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
000032  8a09              LDRH     r1,[r1,#0x10]
000034  8201              STRH     r1,[r0,#0x10]
;;;150    }
000036  bd70              POP      {r4-r6,pc}
;;;151    
                          ENDP


                          AREA ||i.I2S_Init||, CODE, READONLY, ALIGN=1

                  I2S_Init PROC
;;;164    void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
;;;165    {
000000  b5f0              PUSH     {r4-r7,lr}
000002  4605              MOV      r5,r0
000004  460c              MOV      r4,r1
;;;166      u16 tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
000006  2002              MOVS     r0,#2
000008  2100              MOVS     r1,#0
;;;167      u32 tmp = 0;
;;;168      RCC_ClocksTypeDef RCC_Clocks;
;;;169       
;;;170      /* Check the I2S parameters */
;;;171      assert_param(IS_SPI_23_PERIPH(SPIx));
;;;172      assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
;;;173      assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
;;;174      assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
;;;175      assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
;;;176      assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
;;;177      assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
;;;178    
;;;179    /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
;;;180    
;;;181      /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
;;;182      SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
00000a  8baa              LDRH     r2,[r5,#0x1c]
00000c  b085              SUB      sp,sp,#0x14           ;165
00000e  2601              MOVS     r6,#1                 ;166
000010  f24ff24f          MOV      r7,#0xf040
000014  403a              ANDS     r2,r2,r7
000016  83aa              STRH     r2,[r5,#0x1c]
;;;183      SPIx->I2SPR = 0x0002;
000018  8428              STRH     r0,[r5,#0x20]
;;;184      
;;;185      /* Get the I2SCFGR register value */
;;;186      tmpreg = SPIx->I2SCFGR;
00001a  8baf              LDRH     r7,[r5,#0x1c]
;;;187      
;;;188      /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
;;;189      if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
00001c  8922              LDRH     r2,[r4,#8]
00001e  2a02              CMP      r2,#2
000020  d022              BEQ      |L3.104|
;;;190      {
;;;191        i2sodd = (u16)0;
;;;192        i2sdiv = (u16)2;   
;;;193      }
;;;194      /* If the requested audio frequency is not the default, compute the prescaler */
;;;195      else
;;;196      {
;;;197        /* Check the frame length (For the Prescaler computing) */
;;;198        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
000022  88a0              LDRH     r0,[r4,#4]
000024  b100              CBZ      r0,|L3.40|
;;;199        {
;;;200          /* Packet length is 16 bits */
;;;201          packetlength = 1;
;;;202        }
;;;203        else
;;;204        {
;;;205          /* Packet length is 32 bits */
;;;206          packetlength = 2;
000026  2602              MOVS     r6,#2
                  |L3.40|
;;;207        }
;;;208        /* Get System Clock frequency */
;;;209        RCC_GetClocksFreq(&RCC_Clocks);
000028  4668              MOV      r0,sp
00002a  f7fff7ff          BL       RCC_GetClocksFreq
;;;210        
;;;211        /* Compute the Real divider depending on the MCLK output state with a flaoting point */
;;;212        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
00002e  88e0              LDRH     r0,[r4,#6]
000030  210a              MOVS     r1,#0xa
000032  f5b0f5b0          CMP      r0,#0x200
000036  d106              BNE      |L3.70|
;;;213        {
;;;214          /* MCLK output is enabled */
;;;215          tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);
000038  9800              LDR      r0,[sp,#0]
00003a  8922              LDRH     r2,[r4,#8]
00003c  4348              MULS     r0,r1,r0
00003e  0212              LSLS     r2,r2,#8
000040  fbb0fbb0          UDIV     r0,r0,r2
000044  e006              B        |L3.84|
                  |L3.70|
;;;216        }
;;;217        else
;;;218        {
;;;219          /* MCLK output is disabled */
;;;220          tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);
000046  8923              LDRH     r3,[r4,#8]
000048  0170              LSLS     r0,r6,#5
00004a  9a00              LDR      r2,[sp,#0]
00004c  4358              MULS     r0,r3,r0
00004e  434a              MULS     r2,r1,r2
000050  fbb2fbb2          UDIV     r0,r2,r0
                  |L3.84|
000054  1d40              ADDS     r0,r0,#5
000056  b280              UXTH     r0,r0
;;;221        }
;;;222        
;;;223        /* Remove the flaoting point */
;;;224        tmp = tmp/10;  
000058  fbb0fbb0          UDIV     r0,r0,r1
;;;225          
;;;226        /* Check the parity of the divider */
;;;227        i2sodd = (u16)(tmp & (u16)0x0001);
00005c  f000f000          AND      r1,r0,#1
;;;228       
;;;229        /* Compute the i2sdiv prescaler */
;;;230        i2sdiv = (u16)((tmp - i2sodd) / 2);
000060  1a40              SUBS     r0,r0,r1
000062  f3c0f3c0          UBFX     r0,r0,#1,#16
;;;231       
;;;232        /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
;;;233        i2sodd = (u16) (i2sodd << 8);
000066  0209              LSLS     r1,r1,#8
                  |L3.104|
;;;234      }
;;;235      
;;;236      /* Test if the divider is 1 or 0 */
;;;237      if ((i2sdiv < 2) || (i2sdiv > 0xFF))
000068  1e82              SUBS     r2,r0,#2
00006a  2afe              CMP      r2,#0xfe
00006c  d301              BCC      |L3.114|
;;;238      {
;;;239        /* Set the default values */
;;;240        i2sdiv = 2;
00006e  2002              MOVS     r0,#2
;;;241        i2sodd = 0;
000070  2100              MOVS     r1,#0
                  |L3.114|
;;;242      }
;;;243    
;;;244      /* Write to SPIx I2SPR register the computed value */
;;;245      SPIx->I2SPR = (u16)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput);  
000072  88e2              LDRH     r2,[r4,#6]
000074  4308              ORRS     r0,r0,r1
000076  4302              ORRS     r2,r2,r0
000078  842a              STRH     r2,[r5,#0x20]
;;;246     
;;;247      /* Configure the I2S with the SPI_InitStruct values */
;;;248      tmpreg |= (u16)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \
00007a  8820              LDRH     r0,[r4,#0]
00007c  8862              LDRH     r2,[r4,#2]
00007e  88a1              LDRH     r1,[r4,#4]
000080  8963              LDRH     r3,[r4,#0xa]
000082  4310              ORRS     r0,r0,r2
000084  4319              ORRS     r1,r1,r3
000086  4308              ORRS     r0,r0,r1
000088  4338              ORRS     r0,r0,r7
00008a  f440f440          ORR      r0,r0,#0x800
;;;249                      I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \
;;;250                      I2S_InitStruct->I2S_CPOL);
;;;251     
;;;252      /* Write to SPIx I2SCFGR */  
;;;253      SPIx->I2SCFGR = tmpreg;                                    
00008e  83a8              STRH     r0,[r5,#0x1c]