📄 stm32f10x_pwr.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_pwr.o --depend=.\Obj\stm32f10x_pwr.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_pwr.crf ..\..\..\FWLib\library\src\stm32f10x_pwr.c]
THUMB
AREA ||i.PWR_DeInit||, CODE, READONLY, ALIGN=1
PWR_DeInit PROC
;;;67 void PWR_DeInit(void)
;;;68 {
000000 b510 PUSH {r4,lr}
;;;69 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
000002 2101 MOVS r1,#1
000004 070c LSLS r4,r1,#28
000006 4620 MOV r0,r4
000008 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;70 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00000c 4620 MOV r0,r4
00000e e8bde8bd POP {r4,lr}
000012 2100 MOVS r1,#0
000014 f7fff7ff B.W RCC_APB1PeriphResetCmd
;;;71 }
;;;72
ENDP
AREA ||i.PWR_BackupAccessCmd||, CODE, READONLY, ALIGN=2
PWR_BackupAccessCmd PROC
;;;85
;;;86 *(vu32 *) CR_DBP_BB = (u32)NewState;
000000 4901 LDR r1,|L2.8|
000002 6208 STR r0,[r1,#0x20]
;;;87 }
000004 4770 BX lr
;;;88
ENDP
000006 0000 DCW 0x0000
|L2.8|
000008 420e0000 DCD 0x420e0000
AREA ||i.PWR_PVDCmd||, CODE, READONLY, ALIGN=2
PWR_PVDCmd PROC
;;;101
;;;102 *(vu32 *) CR_PVDE_BB = (u32)NewState;
000000 4901 LDR r1,|L3.8|
000002 6108 STR r0,[r1,#0x10]
;;;103 }
000004 4770 BX lr
;;;104
ENDP
000006 0000 DCW 0x0000
|L3.8|
000008 420e0000 DCD 0x420e0000
AREA ||i.PWR_PVDLevelConfig||, CODE, READONLY, ALIGN=2
PWR_PVDLevelConfig PROC
;;;128
;;;129 tmpreg = PWR->CR;
000000 4a03 LDR r2,|L4.16|
000002 6811 LDR r1,[r2,#0]
;;;130
;;;131 /* Clear PLS[7:5] bits */
;;;132 tmpreg &= CR_PLS_Mask;
000004 f021f021 BIC r1,r1,#0xe0
;;;133
;;;134 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
;;;135 tmpreg |= PWR_PVDLevel;
000008 4301 ORRS r1,r1,r0
;;;136
;;;137 /* Store the new value */
;;;138 PWR->CR = tmpreg;
00000a 6011 STR r1,[r2,#0]
;;;139 }
00000c 4770 BX lr
;;;140
ENDP
00000e 0000 DCW 0x0000
|L4.16|
000010 40007000 DCD 0x40007000
AREA ||i.PWR_WakeUpPinCmd||, CODE, READONLY, ALIGN=2
PWR_WakeUpPinCmd PROC
;;;149 void PWR_WakeUpPinCmd(FunctionalState NewState)
;;;150 {
000000 4901 LDR r1,|L5.8|
;;;151 /* Check the parameters */
;;;152 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;153
;;;154 *(vu32 *) CSR_EWUP_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;155 }
000004 4770 BX lr
;;;156
ENDP
000006 0000 DCW 0x0000
|L5.8|
000008 420e00a0 DCD 0x420e00a0
AREA ||i.PWR_EnterSTOPMode||, CODE, READONLY, ALIGN=2
PWR_EnterSTOPMode PROC
;;;181 /* Select the regulator state in STOP mode ---------------------------------*/
;;;182 tmpreg = PWR->CR;
000000 4b08 LDR r3,|L6.36|
000002 681a LDR r2,[r3,#0]
;;;183
;;;184 /* Clear PDDS and LPDS bits */
;;;185 tmpreg &= CR_DS_Mask;
000004 f022f022 BIC r2,r2,#3
;;;186
;;;187 /* Set LPDS bit according to PWR_Regulator value */
;;;188 tmpreg |= PWR_Regulator;
000008 4302 ORRS r2,r2,r0
;;;189
;;;190 /* Store the new value */
;;;191 PWR->CR = tmpreg;
00000a 601a STR r2,[r3,#0]
00000c 4806 LDR r0,|L6.40|
;;;192
;;;193 /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;194 *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
00000e 6802 LDR r2,[r0,#0]
;;;195
;;;196 /* Select STOP mode entry --------------------------------------------------*/
;;;197 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
000010 2901 CMP r1,#1
000012 f042f042 ORR r1,r2,#4 ;194
000016 6001 STR r1,[r0,#0] ;194
000018 d101 BNE |L6.30|
;;;198 {
;;;199 /* Request Wait For Interrupt */
;;;200 __WFI();
00001a f7fff7ff B.W __WFI
|L6.30|
;;;201 }
;;;202 else
;;;203 {
;;;204 /* Request Wait For Event */
;;;205 __WFE();
00001e f7fff7ff B.W __WFE
;;;206 }
;;;207 }
;;;208
ENDP
000022 0000 DCW 0x0000
|L6.36|
000024 40007000 DCD 0x40007000
|L6.40|
000028 e000ed10 DCD 0xe000ed10
AREA ||i.PWR_EnterSTANDBYMode||, CODE, READONLY, ALIGN=2
PWR_EnterSTANDBYMode PROC
;;;218 /* Clear Wake-up flag */
;;;219 PWR->CR |= CR_CWUF_Set;
000000 4807 LDR r0,|L7.32|
000002 6801 LDR r1,[r0,#0]
000004 f041f041 ORR r1,r1,#4
000008 6001 STR r1,[r0,#0]
;;;220
;;;221 /* Select STANDBY mode */
;;;222 PWR->CR |= CR_PDDS_Set;
00000a 6801 LDR r1,[r0,#0]
00000c f041f041 ORR r1,r1,#2
000010 6001 STR r1,[r0,#0]
000012 4804 LDR r0,|L7.36|
;;;223
;;;224 /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;225 *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
000014 6801 LDR r1,[r0,#0]
000016 f041f041 ORR r1,r1,#4
00001a 6001 STR r1,[r0,#0]
;;;226
;;;227 /* Request Wait For Interrupt */
;;;228 __WFI();
00001c f7fff7ff B.W __WFI
;;;229 }
;;;230
ENDP
|L7.32|
000020 40007000 DCD 0x40007000
|L7.36|
000024 e000ed10 DCD 0xe000ed10
AREA ||i.PWR_GetFlagStatus||, CODE, READONLY, ALIGN=2
PWR_GetFlagStatus PROC
;;;248
;;;249 if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
000000 4903 LDR r1,|L8.16|
000002 4602 MOV r2,r0
000004 6849 LDR r1,[r1,#4]
000006 2000 MOVS r0,#0
000008 4211 TST r1,r2
00000a d000 BEQ |L8.14|
;;;250 {
;;;251 bitstatus = SET;
00000c 2001 MOVS r0,#1
|L8.14|
;;;252 }
;;;253 else
;;;254 {
;;;255 bitstatus = RESET;
;;;256 }
;;;257
;;;258 /* Return the flag status */
;;;259 return bitstatus;
;;;260 }
00000e 4770 BX lr
;;;261
ENDP
|L8.16|
000010 40007000 DCD 0x40007000
AREA ||i.PWR_ClearFlag||, CODE, READONLY, ALIGN=2
PWR_ClearFlag PROC
;;;276
;;;277 PWR->CR |= PWR_FLAG << 2;
000000 4902 LDR r1,|L9.12|
000002 680a LDR r2,[r1,#0]
000004 ea42ea42 ORR r0,r2,r0,LSL #2
000008 6008 STR r0,[r1,#0]
;;;278 }
00000a 4770 BX lr
;;;279
ENDP
|L9.12|
00000c 40007000 DCD 0x40007000
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