📄 fsmc_sram.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\fsmc_sram.o --depend=.\Obj\fsmc_sram.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\fsmc_sram.crf ..\..\SRAM\fsmc_sram.c]
THUMB
AREA ||i.FSMC_SRAM_Init||, CODE, READONLY, ALIGN=2
FSMC_SRAM_Init PROC
;;;40 void FSMC_SRAM_Init(void)
;;;41 {
000000 b5f0 PUSH {r4-r7,lr}
000002 b097 SUB sp,sp,#0x5c
;;;42 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
;;;43 FSMC_NORSRAMTimingInitTypeDef p;
;;;44 GPIO_InitTypeDef GPIO_InitStructure;
;;;45
;;;46 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
000004 2101 MOVS r1,#1
000006 f44ff44f MOV r0,#0x1e0
00000a f7fff7ff BL RCC_APB2PeriphClockCmd
;;;47 RCC_APB2Periph_GPIOF, ENABLE);
;;;48
;;;49 /*-- GPIO Configuration ------------------------------------------------------*/
;;;50 /* SRAM Data lines configuration */
;;;51 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00000e f24cf24c MOV r0,#0xc703
000012 f8adf8ad STRH r0,[sp,#0]
;;;52 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
;;;53 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
000016 2018 MOVS r0,#0x18
000018 f88df88d STRB r0,[sp,#3]
;;;54 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
;;;55 GPIO_Init(GPIOD, &GPIO_InitStructure);
00001c 4e30 LDR r6,|L1.224|
00001e 2403 MOVS r4,#3 ;54
000020 f88df88d STRB r4,[sp,#2] ;54
000024 4669 MOV r1,sp
000026 4630 MOV r0,r6
000028 f7fff7ff BL GPIO_Init
;;;56
;;;57 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00002c f64ff64f MOV r0,#0xff80
;;;58 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
;;;59 GPIO_Pin_15;
;;;60 GPIO_Init(GPIOE, &GPIO_InitStructure);
000030 4d2c LDR r5,|L1.228|
000032 f8adf8ad STRH r0,[sp,#0] ;57
000036 4669 MOV r1,sp
000038 4628 MOV r0,r5
00003a f7fff7ff BL GPIO_Init
;;;61
;;;62 /* SRAM Address lines configuration */
;;;63 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00003e f24ff24f MOV r0,#0xf03f
000042 f8adf8ad STRH r0,[sp,#0]
;;;64 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
;;;65 GPIO_Pin_14 | GPIO_Pin_15;
;;;66 GPIO_Init(GPIOF, &GPIO_InitStructure);
000046 4669 MOV r1,sp
000048 4827 LDR r0,|L1.232|
00004a f7fff7ff BL GPIO_Init
;;;67
;;;68 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00004e 203f MOVS r0,#0x3f
;;;69 GPIO_Pin_4 | GPIO_Pin_5;
;;;70 GPIO_Init(GPIOG, &GPIO_InitStructure);
000050 4f26 LDR r7,|L1.236|
000052 f8adf8ad STRH r0,[sp,#0] ;68
000056 4669 MOV r1,sp
000058 4638 MOV r0,r7
00005a f7fff7ff BL GPIO_Init
;;;71
;;;72 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
00005e f44ff44f MOV r0,#0x3800
000062 f8adf8ad STRH r0,[sp,#0]
;;;73 GPIO_Init(GPIOD, &GPIO_InitStructure);
000066 4669 MOV r1,sp
000068 4630 MOV r0,r6
00006a f7fff7ff BL GPIO_Init
;;;74
;;;75 /* NOE and NWE configuration */
;;;76 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
00006e 2030 MOVS r0,#0x30
000070 f8adf8ad STRH r0,[sp,#0]
;;;77 GPIO_Init(GPIOD, &GPIO_InitStructure);
000074 4669 MOV r1,sp
000076 4630 MOV r0,r6
000078 f7fff7ff BL GPIO_Init
;;;78
;;;79 /* NE3 configuration */
;;;80 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
00007c 1528 ASRS r0,r5,#20
00007e f8adf8ad STRH r0,[sp,#0]
;;;81 GPIO_Init(GPIOG, &GPIO_InitStructure);
000082 4669 MOV r1,sp
000084 4638 MOV r0,r7
000086 f7fff7ff BL GPIO_Init
;;;82
;;;83 /* NBL0, NBL1 configuration */
;;;84 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
00008a f8adf8ad STRH r4,[sp,#0]
;;;85 GPIO_Init(GPIOE, &GPIO_InitStructure);
00008e 4669 MOV r1,sp
000090 4628 MOV r0,r5
000092 f7fff7ff BL GPIO_Init
;;;86
;;;87 /*-- FSMC Configuration ------------------------------------------------------*/
;;;88 p.FSMC_AddressSetupTime = 0;
000096 2000 MOVS r0,#0
;;;89 p.FSMC_AddressHoldTime = 0;
;;;90 p.FSMC_DataSetupTime = 2;
000098 2102 MOVS r1,#2
00009a 9001 STR r0,[sp,#4] ;89
;;;91 p.FSMC_BusTurnAroundDuration = 0;
00009c e9cde9cd STRD r0,r1,[sp,#8]
;;;92 p.FSMC_CLKDivision = 0;
0000a0 9004 STR r0,[sp,#0x10]
;;;93 p.FSMC_DataLatency = 0;
0000a2 9005 STR r0,[sp,#0x14]
;;;94 p.FSMC_AccessMode = FSMC_AccessMode_A;
0000a4 9006 STR r0,[sp,#0x18]
;;;95
;;;96 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
0000a6 2104 MOVS r1,#4
;;;97 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
0000a8 e9cde9cd STRD r0,r1,[sp,#0x1c]
;;;98 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
;;;99 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
0000ac 2110 MOVS r1,#0x10
0000ae 9009 STR r0,[sp,#0x24] ;98
;;;100 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
0000b0 e9cde9cd STRD r0,r1,[sp,#0x28]
;;;101 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
0000b4 900c STR r0,[sp,#0x30]
;;;102 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
0000b6 900d STR r0,[sp,#0x34]
;;;103 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
0000b8 900e STR r0,[sp,#0x38]
;;;104 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
0000ba 0209 LSLS r1,r1,#8
;;;105 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
0000bc e9cde9cd STRD r0,r1,[sp,#0x3c]
;;;106 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
0000c0 9011 STR r0,[sp,#0x44]
;;;107 FSMC_NORSRAMInitStructure.FSMC_AsyncWait = FSMC_AsyncWait_Disable;
0000c2 9012 STR r0,[sp,#0x48]
;;;108 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
0000c4 9013 STR r0,[sp,#0x4c]
;;;109 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
0000c6 9014 STR r0,[sp,#0x50]
0000c8 a801 ADD r0,sp,#4
;;;110 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
0000ca 9015 STR r0,[sp,#0x54]
;;;111
;;;112 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
0000cc 9016 STR r0,[sp,#0x58]
0000ce a808 ADD r0,sp,#0x20
0000d0 f7fff7ff BL FSMC_NORSRAMInit
;;;113
;;;114 /* Enable FSMC Bank1_SRAM Bank */
;;;115 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
0000d4 2101 MOVS r1,#1
0000d6 2004 MOVS r0,#4
0000d8 f7fff7ff BL FSMC_NORSRAMCmd
;;;116 }
0000dc b017 ADD sp,sp,#0x5c
0000de bdf0 POP {r4-r7,pc}
;;;117
ENDP
|L1.224|
0000e0 40011400 DCD 0x40011400
|L1.228|
0000e4 40011800 DCD 0x40011800
|L1.232|
0000e8 40011c00 DCD 0x40011c00
|L1.236|
0000ec 40012000 DCD 0x40012000
AREA ||i.FSMC_SRAM_WriteBuffer||, CODE, READONLY, ALIGN=1
FSMC_SRAM_WriteBuffer PROC
;;;129 void FSMC_SRAM_WriteBuffer(u16* pBuffer, u32 WriteAddr, u32 NumHalfwordToWrite)
;;;130 {
000000 b510 PUSH {r4,lr}
|L2.2|
;;;131 for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /* while there is data to write */
000002 2a00 CMP r2,#0
000004 d007 BEQ |L2.22|
;;;132 {
;;;133 /* Transfer data to the memory */
;;;134 *(u16 *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
000006 f830f830 LDRH r4,[r0],#2
00000a f04ff04f MOV r3,#0x68000000
00000e 525c STRH r4,[r3,r1]
;;;135
;;;136 /* Increment the address*/
;;;137 WriteAddr += 2;
000010 1c89 ADDS r1,r1,#2
000012 1e52 SUBS r2,r2,#1 ;131
000014 e7f5 B |L2.2|
|L2.22|
;;;138 }
;;;139 }
000016 bd10 POP {r4,pc}
;;;140
ENDP
AREA ||i.FSMC_SRAM_ReadBuffer||, CODE, READONLY, ALIGN=1
FSMC_SRAM_ReadBuffer PROC
;;;151 void FSMC_SRAM_ReadBuffer(u16* pBuffer, u32 ReadAddr, u32 NumHalfwordToRead)
;;;152 {
000000 b510 PUSH {r4,lr}
|L3.2|
;;;153 for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /* while there is data to read */
000002 2a00 CMP r2,#0
000004 d008 BEQ |L3.24|
;;;154 {
;;;155 /* Read a half-word from the memory */
;;;156 *pBuffer++ = *(vu16*) (Bank1_SRAM3_ADDR + ReadAddr);
000006 f04ff04f MOV r3,#0x68000000
00000a 5a5c LDRH r4,[r3,r1]
00000c 4603 MOV r3,r0
00000e 1c80 ADDS r0,r0,#2
;;;157
;;;158 /* Increment the address*/
;;;159 ReadAddr += 2;
000010 1c89 ADDS r1,r1,#2
000012 801c STRH r4,[r3,#0] ;156
000014 1e52 SUBS r2,r2,#1 ;153
000016 e7f4 B |L3.2|
|L3.24|
;;;160 }
;;;161 }
000018 bd10 POP {r4,pc}
;;;162
ENDP
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