📄 stm32f10x_adc.txt
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;;;1024 /* Calculate the mask to clear */
;;;1025 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
000020 eb01eb01 ADD r4,r1,r1,LSL #1
000024 40a6 LSLS r6,r6,r4
;;;1026 /* Clear the old discontinuous mode channel count */
;;;1027 tmpreg1 &= ~tmpreg2;
000026 43b5 BICS r5,r5,r6
;;;1028 /* Calculate the mask to set */
;;;1029 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
000028 40a3 LSLS r3,r3,r4
;;;1030 /* Set the discontinuous mode channel count */
;;;1031 tmpreg1 |= tmpreg2;
00002a 431d ORRS r5,r5,r3
;;;1032 /* Store the new register value */
;;;1033 ADCx->SMPR2 = tmpreg1;
00002c 6105 STR r5,[r0,#0x10]
|L25.46|
;;;1034 }
;;;1035
;;;1036 /* Rank configuration */
;;;1037 /* Get the old register value */
;;;1038 tmpreg1 = ADCx->JSQR;
00002e 6b83 LDR r3,[r0,#0x38]
;;;1039 /* Get JL value: Number = JL+1 */
;;;1040 tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
000030 f3c3f3c3 UBFX r4,r3,#20,#2
;;;1041 /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
;;;1042 tmpreg2 = JSQR_JSQ_Set << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
000034 1b12 SUBS r2,r2,r4
000036 1c92 ADDS r2,r2,#2
000038 eb02eb02 ADD r2,r2,r2,LSL #2
00003c 241f MOVS r4,#0x1f
00003e 4094 LSLS r4,r4,r2
;;;1043 /* Clear the old JSQx bits for the selected rank */
;;;1044 tmpreg1 &= ~tmpreg2;
000040 43a3 BICS r3,r3,r4
;;;1045 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
;;;1046 tmpreg2 = (u32)ADC_Channel << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
000042 4091 LSLS r1,r1,r2
;;;1047 /* Set the JSQx bits for the selected rank */
;;;1048 tmpreg1 |= tmpreg2;
000044 430b ORRS r3,r3,r1
;;;1049 /* Store the new register value */
;;;1050 ADCx->JSQR = tmpreg1;
000046 6383 STR r3,[r0,#0x38]
;;;1051 }
000048 bd70 POP {r4-r6,pc}
;;;1052
ENDP
AREA ||i.ADC_InjectedSequencerLengthConfig||, CODE, READONLY, ALIGN=1
ADC_InjectedSequencerLengthConfig PROC
;;;1071 /* Get the old register value */
;;;1072 tmpreg1 = ADCx->JSQR;
000000 6b82 LDR r2,[r0,#0x38]
;;;1073 /* Clear the old injected sequnence lenght JL bits */
;;;1074 tmpreg1 &= JSQR_JL_Reset;
;;;1075 /* Set the injected sequnence lenght JL bits */
;;;1076 tmpreg2 = Length - 1;
000002 1e49 SUBS r1,r1,#1
000004 f422f422 BIC r2,r2,#0x300000 ;1074
;;;1077 tmpreg1 |= tmpreg2 << 20;
000008 ea42ea42 ORR r1,r2,r1,LSL #20
;;;1078 /* Store the new register value */
;;;1079 ADCx->JSQR = tmpreg1;
00000c 6381 STR r1,[r0,#0x38]
;;;1080 }
00000e 4770 BX lr
;;;1081
ENDP
AREA ||i.ADC_SetInjectedOffset||, CODE, READONLY, ALIGN=1
ADC_SetInjectedOffset PROC
;;;1105 /* Set the selected injected channel data offset */
;;;1106 *((vu32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;
000000 5042 STR r2,[r0,r1]
;;;1107 }
000002 4770 BX lr
;;;1108
ENDP
AREA ||i.ADC_GetInjectedConversionValue||, CODE, READONLY, ALIGN=1
ADC_GetInjectedConversionValue PROC
;;;1128 /* Returns the selected injected channel conversion data value */
;;;1129 return (u16) (*(vu32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));
000000 4408 ADD r0,r0,r1
000002 6a80 LDR r0,[r0,#0x28]
000004 b280 UXTH r0,r0
;;;1130 }
000006 4770 BX lr
;;;1131
ENDP
AREA ||i.ADC_AnalogWatchdogCmd||, CODE, READONLY, ALIGN=2
ADC_AnalogWatchdogCmd PROC
;;;1164 /* Get the old register value */
;;;1165 tmpreg = ADCx->CR1;
000000 6842 LDR r2,[r0,#4]
;;;1166 /* Clear AWDEN, AWDENJ and AWDSGL bits */
;;;1167 tmpreg &= CR1_AWDMode_Reset;
000002 4b02 LDR r3,|L29.12|
000004 401a ANDS r2,r2,r3
;;;1168 /* Set the analog watchdog enable mode */
;;;1169 tmpreg |= ADC_AnalogWatchdog;
000006 430a ORRS r2,r2,r1
;;;1170 /* Store the new register value */
;;;1171 ADCx->CR1 = tmpreg;
000008 6042 STR r2,[r0,#4]
;;;1172 }
00000a 4770 BX lr
;;;1173
ENDP
|L29.12|
00000c ff3ffdff DCD 0xff3ffdff
AREA ||i.ADC_AnalogWatchdogThresholdsConfig||, CODE, READONLY, ALIGN=1
ADC_AnalogWatchdogThresholdsConfig PROC
;;;1193 /* Set the ADCx high threshold */
;;;1194 ADCx->HTR = HighThreshold;
000000 6241 STR r1,[r0,#0x24]
;;;1195 /* Set the ADCx low threshold */
;;;1196 ADCx->LTR = LowThreshold;
000002 6282 STR r2,[r0,#0x28]
;;;1197 }
000004 4770 BX lr
;;;1198
ENDP
AREA ||i.ADC_AnalogWatchdogSingleChannelConfig||, CODE, READONLY, ALIGN=1
ADC_AnalogWatchdogSingleChannelConfig PROC
;;;1235 /* Get the old register value */
;;;1236 tmpreg = ADCx->CR1;
000000 6842 LDR r2,[r0,#4]
;;;1237 /* Clear the Analog watchdog channel select bits */
;;;1238 tmpreg &= CR1_AWDCH_Reset;
000002 f022f022 BIC r2,r2,#0x1f
;;;1239 /* Set the Analog watchdog channel */
;;;1240 tmpreg |= ADC_Channel;
000006 430a ORRS r2,r2,r1
;;;1241 /* Store the new register value */
;;;1242 ADCx->CR1 = tmpreg;
000008 6042 STR r2,[r0,#4]
;;;1243 }
00000a 4770 BX lr
;;;1244
ENDP
AREA ||i.ADC_TempSensorVrefintCmd||, CODE, READONLY, ALIGN=2
ADC_TempSensorVrefintCmd PROC
;;;1253 void ADC_TempSensorVrefintCmd(FunctionalState NewState)
;;;1254 {
000000 4906 LDR r1,|L32.28|
;;;1255 /* Check the parameters */
;;;1256 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1257
;;;1258 if (NewState != DISABLE)
000002 2800 CMP r0,#0
;;;1259 {
;;;1260 /* Enable the temperature sensor and Vrefint channel*/
;;;1261 ADC1->CR2 |= CR2_TSVREFE_Set;
000004 f8d1f8d1 LDR r0,[r1,#0x408]
000008 d002 BEQ |L32.16|
00000a f440f440 ORR r0,r0,#0x800000
00000e e001 B |L32.20|
|L32.16|
;;;1262 }
;;;1263 else
;;;1264 {
;;;1265 /* Disable the temperature sensor and Vrefint channel*/
;;;1266 ADC1->CR2 &= CR2_TSVREFE_Reset;
000010 f420f420 BIC r0,r0,#0x800000
|L32.20|
000014 f8c1f8c1 STR r0,[r1,#0x408] ;1261
;;;1267 }
;;;1268 }
000018 4770 BX lr
;;;1269
ENDP
00001a 0000 DCW 0x0000
|L32.28|
00001c 40012000 DCD 0x40012000
AREA ||i.ADC_GetFlagStatus||, CODE, READONLY, ALIGN=1
ADC_GetFlagStatus PROC
;;;1284 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)
;;;1285 {
000000 4602 MOV r2,r0
;;;1286 FlagStatus bitstatus = RESET;
;;;1287
;;;1288 /* Check the parameters */
;;;1289 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1290 assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
;;;1291
;;;1292 /* Check the status of the specified ADC flag */
;;;1293 if ((ADCx->SR & ADC_FLAG) != (u8)RESET)
000002 6812 LDR r2,[r2,#0]
000004 2000 MOVS r0,#0 ;1286
000006 420a TST r2,r1
000008 d000 BEQ |L33.12|
;;;1294 {
;;;1295 /* ADC_FLAG is set */
;;;1296 bitstatus = SET;
00000a 2001 MOVS r0,#1
|L33.12|
;;;1297 }
;;;1298 else
;;;1299 {
;;;1300 /* ADC_FLAG is reset */
;;;1301 bitstatus = RESET;
;;;1302 }
;;;1303
;;;1304 /* Return the ADC_FLAG status */
;;;1305 return bitstatus;
;;;1306 }
00000c 4770 BX lr
;;;1307
ENDP
AREA ||i.ADC_ClearFlag||, CODE, READONLY, ALIGN=1
ADC_ClearFlag PROC
;;;1328 /* Clear the selected ADC flags */
;;;1329 ADCx->SR = ~(u32)ADC_FLAG;
000000 43c9 MVNS r1,r1
000002 6001 STR r1,[r0,#0]
;;;1330 }
000004 4770 BX lr
;;;1331
ENDP
AREA ||i.ADC_GetITStatus||, CODE, READONLY, ALIGN=1
ADC_GetITStatus PROC
;;;1344 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT)
;;;1345 {
000000 b530 PUSH {r4,r5,lr}
000002 4602 MOV r2,r0
;;;1346 ITStatus bitstatus = RESET;
000004 2000 MOVS r0,#0
;;;1347 u32 itmask = 0, enablestatus = 0;
;;;1348
;;;1349 /* Check the parameters */
;;;1350 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1351 assert_param(IS_ADC_GET_IT(ADC_IT));
;;;1352
;;;1353 /* Get the ADC IT index */
;;;1354 itmask = ADC_IT >> 8;
;;;1355
;;;1356 /* Get the ADC_IT enable bit status */
;;;1357 enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;
000006 6854 LDR r4,[r2,#4]
000008 0a0b LSRS r3,r1,#8 ;1354
00000a b2cd UXTB r5,r1
;;;1358
;;;1359 /* Check the status of the specified ADC interrupt */
;;;1360 if (((ADCx->SR & itmask) != (u32)RESET) && enablestatus)
00000c 6811 LDR r1,[r2,#0]
00000e 402c ANDS r4,r4,r5 ;1357
000010 4219 TST r1,r3
000012 d002 BEQ |L35.26|
000014 2c00 CMP r4,#0
000016 d000 BEQ |L35.26|
;;;1361 {
;;;1362 /* ADC_IT is set */
;;;1363 bitstatus = SET;
000018 2001 MOVS r0,#1
|L35.26|
;;;1364 }
;;;1365 else
;;;1366 {
;;;1367 /* ADC_IT is reset */
;;;1368 bitstatus = RESET;
;;;1369 }
;;;1370
;;;1371 /* Return the ADC_IT status */
;;;1372 return bitstatus;
;;;1373 }
00001a bd30 POP {r4,r5,pc}
;;;1374
ENDP
AREA ||i.ADC_ClearITPendingBit||, CODE, READONLY, ALIGN=1
ADC_ClearITPendingBit PROC
;;;1398 /* Clear the selected ADC interrupt pending bits */
;;;1399 ADCx->SR = ~(u32)itmask;
000000 ea6fea6f MVN r1,r1,LSR #8
000004 6001 STR r1,[r0,#0]
;;;1400 }
000006 4770 BX lr
;;;1401
ENDP
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