stm32f10x_adc.txt

STM32外部SRAM用作datamemery的程序 开发环境MDK

;;;385        bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L8.12|
;;;386      }
;;;387      else
;;;388      {
;;;389        /* RSTCAL bit is reset */
;;;390        bitstatus = RESET;
;;;391      }
;;;392    
;;;393      /* Return the RSTCAL bit status */
;;;394      return  bitstatus;
;;;395    }
00000c  4770              BX       lr
;;;396    
                          ENDP


                          AREA ||i.ADC_StartCalibration||, CODE, READONLY, ALIGN=1

                  ADC_StartCalibration PROC
;;;409      /* Enable the selected ADC calibration process */  
;;;410      ADCx->CR2 |= CR2_CAL_Set;
000000  6881              LDR      r1,[r0,#8]
000002  f041f041          ORR      r1,r1,#4
000006  6081              STR      r1,[r0,#8]
;;;411    }
000008  4770              BX       lr
;;;412    
                          ENDP


                          AREA ||i.ADC_GetCalibrationStatus||, CODE, READONLY, ALIGN=1

                  ADC_GetCalibrationStatus PROC
;;;420    FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
;;;421    {
000000  4601              MOV      r1,r0
;;;422      FlagStatus bitstatus = RESET;
;;;423    
;;;424      /* Check the parameters */
;;;425      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;426    
;;;427      /* Check the status of CAL bit */
;;;428      if ((ADCx->CR2 & CR2_CAL_Set) != (u32)RESET)
000002  6889              LDR      r1,[r1,#8]
000004  2000              MOVS     r0,#0                 ;422
000006  0749              LSLS     r1,r1,#29
000008  d500              BPL      |L10.12|
;;;429      {
;;;430        /* CAL bit is set: calibration on going */
;;;431        bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L10.12|
;;;432      }
;;;433      else
;;;434      {
;;;435        /* CAL bit is reset: end of calibration */
;;;436        bitstatus = RESET;
;;;437      }
;;;438    
;;;439      /* Return the CAL bit status */
;;;440      return  bitstatus;
;;;441    }
00000c  4770              BX       lr
;;;442    
                          ENDP


                          AREA ||i.ADC_SoftwareStartConvCmd||, CODE, READONLY, ALIGN=1

                  ADC_SoftwareStartConvCmd PROC
;;;457    
;;;458      if (NewState != DISABLE)
000000  2900              CMP      r1,#0
;;;459      {
;;;460        /* Enable the selected ADC conversion on external event and start the selected
;;;461           ADC conversion */
;;;462        ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
000002  6881              LDR      r1,[r0,#8]
000004  d002              BEQ      |L11.12|
000006  f441f441          ORR      r1,r1,#0x500000
00000a  e001              B        |L11.16|
                  |L11.12|
;;;463      }
;;;464      else
;;;465      {
;;;466        /* Disable the selected ADC conversion on external event and stop the selected
;;;467           ADC conversion */
;;;468        ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
00000c  f421f421          BIC      r1,r1,#0x500000
                  |L11.16|
000010  6081              STR      r1,[r0,#8]            ;462
;;;469      }
;;;470    }
000012  4770              BX       lr
;;;471    
                          ENDP


                          AREA ||i.ADC_GetSoftwareStartConvStatus||, CODE, READONLY, ALIGN=1

                  ADC_GetSoftwareStartConvStatus PROC
;;;479    FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
;;;480    {
000000  4601              MOV      r1,r0
;;;481      FlagStatus bitstatus = RESET;
;;;482    
;;;483      /* Check the parameters */
;;;484      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;485    
;;;486      /* Check the status of SWSTART bit */
;;;487      if ((ADCx->CR2 & CR2_SWSTART_Set) != (u32)RESET)
000002  6889              LDR      r1,[r1,#8]
000004  2000              MOVS     r0,#0                 ;481
000006  0249              LSLS     r1,r1,#9
000008  d500              BPL      |L12.12|
;;;488      {
;;;489        /* SWSTART bit is set */
;;;490        bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L12.12|
;;;491      }
;;;492      else
;;;493      {
;;;494        /* SWSTART bit is reset */
;;;495        bitstatus = RESET;
;;;496      }
;;;497    
;;;498      /* Return the SWSTART bit status */
;;;499      return  bitstatus;
;;;500    }
00000c  4770              BX       lr
;;;501    
                          ENDP


                          AREA ||i.ADC_DiscModeChannelCountConfig||, CODE, READONLY, ALIGN=1

                  ADC_DiscModeChannelCountConfig PROC
;;;521      /* Get the old register value */
;;;522      tmpreg1 = ADCx->CR1;
000000  6842              LDR      r2,[r0,#4]
;;;523      /* Clear the old discontinuous mode channel count */
;;;524      tmpreg1 &= CR1_DISCNUM_Reset;
;;;525      /* Set the discontinuous mode channel count */
;;;526      tmpreg2 = Number - 1;
000002  1e49              SUBS     r1,r1,#1
000004  f422f422          BIC      r2,r2,#0xe000         ;524
;;;527      tmpreg1 |= tmpreg2 << 13;
000008  ea42ea42          ORR      r1,r2,r1,LSL #13
;;;528      /* Store the new register value */
;;;529      ADCx->CR1 = tmpreg1;
00000c  6041              STR      r1,[r0,#4]
;;;530    }
00000e  4770              BX       lr
;;;531    
                          ENDP


                          AREA ||i.ADC_DiscModeCmd||, CODE, READONLY, ALIGN=1

                  ADC_DiscModeCmd PROC
;;;548    
;;;549      if (NewState != DISABLE)
000000  2900              CMP      r1,#0
;;;550      {
;;;551        /* Enable the selected ADC regular discontinuous mode */
;;;552        ADCx->CR1 |= CR1_DISCEN_Set;
000002  6841              LDR      r1,[r0,#4]
000004  d002              BEQ      |L14.12|
000006  f441f441          ORR      r1,r1,#0x800
00000a  e001              B        |L14.16|
                  |L14.12|
;;;553      }
;;;554      else
;;;555      {
;;;556        /* Disable the selected ADC regular discontinuous mode */
;;;557        ADCx->CR1 &= CR1_DISCEN_Reset;
00000c  f421f421          BIC      r1,r1,#0x800
                  |L14.16|
000010  6041              STR      r1,[r0,#4]            ;552
;;;558      }
;;;559    }
000012  4770              BX       lr
;;;560    
                          ENDP


                          AREA ||i.ADC_RegularChannelConfig||, CODE, READONLY, ALIGN=1

                  ADC_RegularChannelConfig PROC
;;;602    void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
;;;603    {
000000  b570              PUSH     {r4-r6,lr}
000002  2607              MOVS     r6,#7
;;;604      u32 tmpreg1 = 0, tmpreg2 = 0;
;;;605    
;;;606      /* Check the parameters */
;;;607      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;608      assert_param(IS_ADC_CHANNEL(ADC_Channel));
;;;609      assert_param(IS_ADC_REGULAR_RANK(Rank));
;;;610      assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
;;;611    
;;;612      /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
;;;613      if (ADC_Channel > ADC_Channel_9)
000004  2909              CMP      r1,#9
000006  d90a              BLS      |L15.30|
;;;614      {
;;;615        /* Get the old register value */
;;;616        tmpreg1 = ADCx->SMPR1;
000008  68c5              LDR      r5,[r0,#0xc]
;;;617        /* Calculate the mask to clear */
;;;618        tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
00000a  f1a1f1a1          SUB      r4,r1,#0xa
00000e  eb04eb04          ADD      r4,r4,r4,LSL #1
000012  40a6              LSLS     r6,r6,r4
;;;619        /* Clear the old discontinuous mode channel count */
;;;620        tmpreg1 &= ~tmpreg2;
000014  43b5              BICS     r5,r5,r6
;;;621        /* Calculate the mask to set */
;;;622        tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
000016  40a3              LSLS     r3,r3,r4
;;;623        /* Set the discontinuous mode channel count */
;;;624        tmpreg1 |= tmpreg2;
000018  431d              ORRS     r5,r5,r3
;;;625        /* Store the new register value */
;;;626        ADCx->SMPR1 = tmpreg1;
00001a  60c5              STR      r5,[r0,#0xc]
00001c  e007              B        |L15.46|
                  |L15.30|
;;;627      }
;;;628      else /* ADC_Channel include in ADC_Channel_[0..9] */
;;;629      {
;;;630        /* Get the old register value */
;;;631        tmpreg1 = ADCx->SMPR2;
00001e  6905              LDR      r5,[r0,#0x10]
;;;632        /* Calculate the mask to clear */
;;;633        tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
000020  eb01eb01          ADD      r4,r1,r1,LSL #1
000024  40a6              LSLS     r6,r6,r4
;;;634        /* Clear the old discontinuous mode channel count */
;;;635        tmpreg1 &= ~tmpreg2;
000026  43b5              BICS     r5,r5,r6
;;;636        /* Calculate the mask to set */
;;;637        tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
000028  40a3              LSLS     r3,r3,r4
;;;638        /* Set the discontinuous mode channel count */
;;;639        tmpreg1 |= tmpreg2;
00002a  431d              ORRS     r5,r5,r3
;;;640        /* Store the new register value */
;;;641        ADCx->SMPR2 = tmpreg1;
00002c  6105              STR      r5,[r0,#0x10]
                  |L15.46|
00002e  231f              MOVS     r3,#0x1f
;;;642      }
;;;643      /* For Rank 1 to 6 */
;;;644      if (Rank < 7)
000030  2a07              CMP      r2,#7
000032  d209              BCS      |L15.72|
;;;645      {
;;;646        /* Get the old register value */
;;;647        tmpreg1 = ADCx->SQR3;
000034  6b44              LDR      r4,[r0,#0x34]
;;;648        /* Calculate the mask to clear */
;;;649        tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
000036  1e52              SUBS     r2,r2,#1
000038  eb02eb02          ADD      r2,r2,r2,LSL #2
00003c  4093              LSLS     r3,r3,r2
;;;650        /* Clear the old SQx bits for the selected rank */
;;;651        tmpreg1 &= ~tmpreg2;
00003e  439c              BICS     r4,r4,r3
;;;652        /* Calculate the mask to set */
;;;653        tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
000040  4091              LSLS     r1,r1,r2
;;;654        /* Set the SQx bits for the selected rank */
;;;655        tmpreg1 |= tmpreg2;
000042  430c              ORRS     r4,r4,r1
;;;656        /* Store the new register value */
;;;657        ADCx->SQR3 = tmpreg1;
000044  6344              STR      r4,[r0,#0x34]
;;;658      }
;;;659      /* For Rank 7 to 12 */
;;;660      else if (Rank < 13)
;;;661      {
;;;662        /* Get the old register value */
;;;663        tmpreg1 = ADCx->SQR2;
;;;664        /* Calculate the mask to clear */
;;;665        tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
;;;666        /* Clear the old SQx bits for the selected rank */
;;;667        tmpreg1 &= ~tmpreg2;
;;;668        /* Calculate the mask to set */
;;;669        tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
;;;670        /* Set the SQx bits for the selected rank */
;;;671        tmpreg1 |= tmpreg2;
;;;672        /* Store the new register value */
;;;673        ADCx->SQR2 = tmpreg1;
;;;674      }
;;;675      /* For Rank 13 to 16 */
;;;676      else
;;;677      {
;;;678        /* Get the old register value */
;;;679        tmpreg1 = ADCx->SQR1;
;;;680        /* Calculate the mask to clear */
;;;681        tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
;;;682        /* Clear the old SQx bits for the selected rank */
;;;683        tmpreg1 &= ~tmpreg2;
;;;684        /* Calculate the mask to set */
;;;685        tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13));
;;;686        /* Set the SQx bits for the selected rank */
;;;687        tmpreg1 |= tmpreg2;
;;;688        /* Store the new register value */
;;;689        ADCx->SQR1 = tmpreg1;