📄 stm32f10x_adc.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_adc.o --depend=.\Obj\stm32f10x_adc.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_adc.crf ..\..\..\FWLib\library\src\stm32f10x_adc.c]
THUMB
AREA ||i.ADC_DeInit||, CODE, READONLY, ALIGN=2
ADC_DeInit PROC
;;;134
;;;135 switch (*(u32*)&ADCx)
000000 490d LDR r1,|L1.56|
000002 b510 PUSH {r4,lr}
000004 1840 ADDS r0,r0,r1
000006 d011 BEQ |L1.44|
000008 f44ff44f MOV r4,#0x400
00000c 42a0 CMP r0,r4
00000e d010 BEQ |L1.50|
000010 f5b0f5b0 CMP r0,#0x1800
000014 d10f BNE |L1.54|
;;;136 {
;;;137 case ADC1_BASE:
;;;138 /* Enable ADC1 reset state */
;;;139 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
;;;140 /* Release ADC1 from reset state */
;;;141 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
;;;142 break;
;;;143
;;;144 case ADC2_BASE:
;;;145 /* Enable ADC2 reset state */
;;;146 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
;;;147 /* Release ADC2 from reset state */
;;;148 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
;;;149 break;
;;;150
;;;151 case ADC3_BASE:
;;;152 /* Enable ADC3 reset state */
;;;153 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
000016 2101 MOVS r1,#1
000018 03cc LSLS r4,r1,#15
|L1.26|
00001a 4620 MOV r0,r4
00001c f7fff7ff BL RCC_APB2PeriphResetCmd
;;;154 /* Release ADC3 from reset state */
;;;155 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
000020 4620 MOV r0,r4
000022 e8bde8bd POP {r4,lr}
000026 2100 MOVS r1,#0
000028 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.44|
00002c 2101 MOVS r1,#1 ;139
00002e 024c LSLS r4,r1,#9 ;139
000030 e7f3 B |L1.26|
|L1.50|
000032 2101 MOVS r1,#1 ;146
000034 e7f1 B |L1.26|
|L1.54|
;;;156 break;
;;;157
;;;158 default:
;;;159 break;
;;;160 }
;;;161 }
000036 bd10 POP {r4,pc}
;;;162
ENDP
|L1.56|
000038 bffedc00 DCD 0xbffedc00
AREA ||i.ADC_Init||, CODE, READONLY, ALIGN=2
ADC_Init PROC
;;;174 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
;;;175 {
000000 b530 PUSH {r4,r5,lr}
;;;176 u32 tmpreg1 = 0;
;;;177 u8 tmpreg2 = 0;
;;;178
;;;179 /* Check the parameters */
;;;180 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;181 assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
;;;182 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
;;;183 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
;;;184 assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
;;;185 assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
;;;186 assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
;;;187
;;;188 /*---------------------------- ADCx CR1 Configuration -----------------*/
;;;189 /* Get the ADCx CR1 value */
;;;190 tmpreg1 = ADCx->CR1;
000002 6842 LDR r2,[r0,#4]
;;;191 /* Clear DUALMOD and SCAN bits */
;;;192 tmpreg1 &= CR1_CLEAR_Mask;
000004 4b0e LDR r3,|L2.64|
;;;193 /* Configure ADCx: Dual mode and scan conversion mode */
;;;194 /* Set DUALMOD bits according to ADC_Mode value */
;;;195 /* Set SCAN bit according to ADC_ScanConvMode value */
;;;196 tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
000006 790c LDRB r4,[r1,#4]
000008 401a ANDS r2,r2,r3 ;192
00000a 680b LDR r3,[r1,#0]
00000c ea42ea42 ORR r2,r2,r4,LSL #8
000010 4313 ORRS r3,r3,r2
;;;197 /* Write to ADCx CR1 */
;;;198 ADCx->CR1 = tmpreg1;
000012 6043 STR r3,[r0,#4]
;;;199
;;;200 /*---------------------------- ADCx CR2 Configuration -----------------*/
;;;201 /* Get the ADCx CR2 value */
;;;202 tmpreg1 = ADCx->CR2;
000014 6882 LDR r2,[r0,#8]
;;;203 /* Clear CONT, ALIGN and EXTSEL bits */
;;;204 tmpreg1 &= CR2_CLEAR_Mask;
000016 4b0b LDR r3,|L2.68|
;;;205 /* Configure ADCx: external trigger event and continuous conversion mode */
;;;206 /* Set ALIGN bit according to ADC_DataAlign value */
;;;207 /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
;;;208 /* Set CONT bit according to ADC_ContinuousConvMode value */
;;;209 tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
000018 794d LDRB r5,[r1,#5]
00001a 401a ANDS r2,r2,r3 ;204
00001c e9d1e9d1 LDRD r4,r3,[r1,#8]
000020 ea42ea42 ORR r2,r2,r5,LSL #1
000024 4323 ORRS r3,r3,r4
000026 4313 ORRS r3,r3,r2
;;;210 ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
;;;211 /* Write to ADCx CR2 */
;;;212 ADCx->CR2 = tmpreg1;
000028 6083 STR r3,[r0,#8]
;;;213
;;;214 /*---------------------------- ADCx SQR1 Configuration -----------------*/
;;;215 /* Get the ADCx SQR1 value */
;;;216 tmpreg1 = ADCx->SQR1;
00002a 6ac2 LDR r2,[r0,#0x2c]
;;;217 /* Clear L bits */
;;;218 tmpreg1 &= SQR1_CLEAR_Mask;
;;;219 /* Configure ADCx: regular channel sequence length */
;;;220 /* Set L bits according to ADC_NbrOfChannel value */
;;;221 tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);
00002c 7c09 LDRB r1,[r1,#0x10]
00002e f422f422 BIC r2,r2,#0xf00000 ;218
000032 1e49 SUBS r1,r1,#1
000034 b2c9 UXTB r1,r1
;;;222 tmpreg1 |= ((u32)tmpreg2 << 20);
000036 ea42ea42 ORR r1,r2,r1,LSL #20
;;;223 /* Write to ADCx SQR1 */
;;;224 ADCx->SQR1 = tmpreg1;
00003a 62c1 STR r1,[r0,#0x2c]
;;;225 }
00003c bd30 POP {r4,r5,pc}
;;;226
ENDP
00003e 0000 DCW 0x0000
|L2.64|
000040 fff0feff DCD 0xfff0feff
|L2.68|
000044 fff1f7fd DCD 0xfff1f7fd
AREA ||i.ADC_StructInit||, CODE, READONLY, ALIGN=1
ADC_StructInit PROC
;;;238 /* Initialize the ADC_Mode member */
;;;239 ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
000000 2100 MOVS r1,#0
;;;240
;;;241 /* initialize the ADC_ScanConvMode member */
;;;242 ADC_InitStruct->ADC_ScanConvMode = DISABLE;
000002 6001 STR r1,[r0,#0]
000004 7101 STRB r1,[r0,#4]
;;;243
;;;244 /* Initialize the ADC_ContinuousConvMode member */
;;;245 ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
000006 7141 STRB r1,[r0,#5]
;;;246
;;;247 /* Initialize the ADC_ExternalTrigConv member */
;;;248 ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
;;;249
;;;250 /* Initialize the ADC_DataAlign member */
;;;251 ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
000008 6081 STR r1,[r0,#8]
;;;252
;;;253 /* Initialize the ADC_NbrOfChannel member */
;;;254 ADC_InitStruct->ADC_NbrOfChannel = 1;
00000a 60c1 STR r1,[r0,#0xc]
00000c 2101 MOVS r1,#1
00000e 7401 STRB r1,[r0,#0x10]
;;;255 }
000010 4770 BX lr
;;;256
ENDP
AREA ||i.ADC_Cmd||, CODE, READONLY, ALIGN=1
ADC_Cmd PROC
;;;271
;;;272 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;273 {
;;;274 /* Set the ADON bit to wake up the ADC from power down mode */
;;;275 ADCx->CR2 |= CR2_ADON_Set;
000002 6881 LDR r1,[r0,#8]
000004 d002 BEQ |L4.12|
000006 f041f041 ORR r1,r1,#1
00000a e001 B |L4.16|
|L4.12|
;;;276 }
;;;277 else
;;;278 {
;;;279 /* Disable the selected ADC peripheral */
;;;280 ADCx->CR2 &= CR2_ADON_Reset;
00000c f021f021 BIC r1,r1,#1
|L4.16|
000010 6081 STR r1,[r0,#8] ;275
;;;281 }
;;;282 }
000012 4770 BX lr
;;;283
ENDP
AREA ||i.ADC_DMACmd||, CODE, READONLY, ALIGN=1
ADC_DMACmd PROC
;;;299
;;;300 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;301 {
;;;302 /* Enable the selected ADC DMA request */
;;;303 ADCx->CR2 |= CR2_DMA_Set;
000002 6881 LDR r1,[r0,#8]
000004 d002 BEQ |L5.12|
000006 f441f441 ORR r1,r1,#0x100
00000a e001 B |L5.16|
|L5.12|
;;;304 }
;;;305 else
;;;306 {
;;;307 /* Disable the selected ADC DMA request */
;;;308 ADCx->CR2 &= CR2_DMA_Reset;
00000c f421f421 BIC r1,r1,#0x100
|L5.16|
000010 6081 STR r1,[r0,#8] ;303
;;;309 }
;;;310 }
000012 4770 BX lr
;;;311
ENDP
AREA ||i.ADC_ITConfig||, CODE, READONLY, ALIGN=1
ADC_ITConfig PROC
;;;338
;;;339 if (NewState != DISABLE)
000000 2a00 CMP r2,#0
;;;340 {
;;;341 /* Enable the selected ADC interrupts */
;;;342 ADCx->CR1 |= itmask;
000002 6842 LDR r2,[r0,#4]
000004 b2c9 UXTB r1,r1
000006 d001 BEQ |L6.12|
000008 430a ORRS r2,r2,r1
00000a e000 B |L6.14|
|L6.12|
;;;343 }
;;;344 else
;;;345 {
;;;346 /* Disable the selected ADC interrupts */
;;;347 ADCx->CR1 &= (~(u32)itmask);
00000c 438a BICS r2,r2,r1
|L6.14|
00000e 6042 STR r2,[r0,#4] ;342
;;;348 }
;;;349 }
000010 4770 BX lr
;;;350
ENDP
AREA ||i.ADC_ResetCalibration||, CODE, READONLY, ALIGN=1
ADC_ResetCalibration PROC
;;;363 /* Resets the selected ADC calibartion registers */
;;;364 ADCx->CR2 |= CR2_RSTCAL_Set;
000000 6881 LDR r1,[r0,#8]
000002 f041f041 ORR r1,r1,#8
000006 6081 STR r1,[r0,#8]
;;;365 }
000008 4770 BX lr
;;;366
ENDP
AREA ||i.ADC_GetResetCalibrationStatus||, CODE, READONLY, ALIGN=1
ADC_GetResetCalibrationStatus PROC
;;;374 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
;;;375 {
000000 4601 MOV r1,r0
;;;376 FlagStatus bitstatus = RESET;
;;;377
;;;378 /* Check the parameters */
;;;379 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;380
;;;381 /* Check the status of RSTCAL bit */
;;;382 if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u32)RESET)
000002 6889 LDR r1,[r1,#8]
000004 2000 MOVS r0,#0 ;376
000006 0709 LSLS r1,r1,#28
000008 d500 BPL |L8.12|
;;;383 {
;;;384 /* RSTCAL bit is set */
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