📄 fsmc_nand.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\fsmc_nand.o --depend=.\Obj\fsmc_nand.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\fsmc_nand.crf ..\..\source\fsmc_nand.c]
THUMB
AREA ||i.FSMC_NAND_Init||, CODE, READONLY, ALIGN=2
FSMC_NAND_Init PROC
;;;41 void FSMC_NAND_Init(void)
;;;42 {
000000 b570 PUSH {r4-r6,lr}
000002 b090 SUB sp,sp,#0x40
;;;43 GPIO_InitTypeDef GPIO_InitStructure;
;;;44 FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
;;;45 FSMC_NAND_PCCARDTimingInitTypeDef p;
;;;46
;;;47 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
000004 2101 MOVS r1,#1
000006 f44ff44f MOV r0,#0x1e0
00000a f7fff7ff BL RCC_APB2PeriphClockCmd
;;;48 RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
;;;49
;;;50 /*-- GPIO Configuration ------------------------------------------------------*/
;;;51 /* CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
;;;52 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
00000e f64df64d MOV r0,#0xd8b3
000012 f8adf8ad STRH r0,[sp,#0x3c]
;;;53 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
;;;54 GPIO_Pin_7;
;;;55 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
000016 2503 MOVS r5,#3
000018 f88df88d STRB r5,[sp,#0x3e]
;;;56 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00001c 2018 MOVS r0,#0x18
;;;57
;;;58 GPIO_Init(GPIOD, &GPIO_InitStructure);
00001e 4e1f LDR r6,|L1.156|
000020 f88df88d STRB r0,[sp,#0x3f] ;56
000024 a90f ADD r1,sp,#0x3c
000026 4630 MOV r0,r6
000028 f7fff7ff BL GPIO_Init
;;;59
;;;60 /* D4->D7 NAND pin configuration */
;;;61 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
00002c f44ff44f MOV r0,#0x780
000030 f8adf8ad STRH r0,[sp,#0x3c]
;;;62
;;;63 GPIO_Init(GPIOE, &GPIO_InitStructure);
000034 a90f ADD r1,sp,#0x3c
000036 481a LDR r0,|L1.160|
000038 f7fff7ff BL GPIO_Init
;;;64
;;;65
;;;66 /* NWAIT NAND pin configuration */
;;;67 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00003c 2440 MOVS r4,#0x40
00003e f8adf8ad STRH r4,[sp,#0x3c]
;;;68 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
000042 f88df88d STRB r5,[sp,#0x3e]
;;;69 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
000046 2048 MOVS r0,#0x48
000048 f88df88d STRB r0,[sp,#0x3f]
;;;70
;;;71 GPIO_Init(GPIOD, &GPIO_InitStructure);
00004c a90f ADD r1,sp,#0x3c
00004e 4630 MOV r0,r6
000050 f7fff7ff BL GPIO_Init
;;;72
;;;73 /* INT2 NAND pin configuration */
;;;74 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
000054 f8adf8ad STRH r4,[sp,#0x3c]
;;;75 GPIO_Init(GPIOG, &GPIO_InitStructure);
000058 a90f ADD r1,sp,#0x3c
00005a 4812 LDR r0,|L1.164|
00005c f7fff7ff BL GPIO_Init
;;;76
;;;77 /*-- FSMC Configuration ------------------------------------------------------*/
;;;78 p.FSMC_SetupTime = 0x1;
000060 2001 MOVS r0,#1
;;;79 p.FSMC_WaitSetupTime = 0x3;
;;;80 p.FSMC_HoldSetupTime = 0x2;
;;;81 p.FSMC_HiZSetupTime = 0x1;
000062 e9cde9cd STRD r0,r5,[sp,#4]
000066 2102 MOVS r1,#2 ;80
;;;82
;;;83 FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
000068 e9cde9cd STRD r1,r0,[sp,#0xc]
00006c 2010 MOVS r0,#0x10
;;;84 FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
;;;85 FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00006e e9cde9cd STRD r0,r1,[sp,#0x14]
000072 2000 MOVS r0,#0
;;;86 FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
;;;87 FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
;;;88 FSMC_NANDInitStructure.FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
000074 e9cde9cd STRD r0,r4,[sp,#0x1c]
000078 0409 LSLS r1,r1,#16 ;87
;;;89 FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
00007a e9cde9cd STRD r1,r0,[sp,#0x24]
;;;90 FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
00007e 900b STR r0,[sp,#0x2c]
;;;91 FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
000080 900c STR r0,[sp,#0x30]
000082 a801 ADD r0,sp,#4
;;;92 FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
000084 900d STR r0,[sp,#0x34]
;;;93
;;;94 FSMC_NANDInit(&FSMC_NANDInitStructure);
000086 900e STR r0,[sp,#0x38]
000088 a805 ADD r0,sp,#0x14
00008a f7fff7ff BL FSMC_NANDInit
;;;95
;;;96 /* FSMC NAND Bank Cmd Test */
;;;97 FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
00008e 2101 MOVS r1,#1
000090 2010 MOVS r0,#0x10
000092 f7fff7ff BL FSMC_NANDCmd
;;;98 }
000096 b010 ADD sp,sp,#0x40
000098 bd70 POP {r4-r6,pc}
;;;99
ENDP
00009a 0000 DCW 0x0000
|L1.156|
00009c 40011400 DCD 0x40011400
|L1.160|
0000a0 40011800 DCD 0x40011800
|L1.164|
0000a4 40012000 DCD 0x40012000
AREA ||i.FSMC_NAND_ReadID||, CODE, READONLY, ALIGN=2
FSMC_NAND_ReadID PROC
;;;112 /* Send Command to the command area */
;;;113 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
000000 4a08 LDR r2,|L2.36|
000002 2190 MOVS r1,#0x90
000004 7011 STRB r1,[r2,#0]
;;;114 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
000006 4a08 LDR r2,|L2.40|
000008 2100 MOVS r1,#0
00000a 7011 STRB r1,[r2,#0]
;;;115
;;;116 /* Sequence to read ID from NAND flash */
;;;117 data = *(vu32 *)(Bank_NAND_ADDR | DATA_AREA);
00000c f04ff04f MOV r1,#0x70000000
000010 6809 LDR r1,[r1,#0]
;;;118
;;;119 NAND_ID->Maker_ID = ADDR_1st_CYCLE (data);
000012 7001 STRB r1,[r0,#0]
;;;120 NAND_ID->Device_ID = ADDR_2nd_CYCLE (data);
000014 0a0a LSRS r2,r1,#8
000016 7042 STRB r2,[r0,#1]
;;;121 NAND_ID->Third_ID = ADDR_3rd_CYCLE (data);
000018 0c0a LSRS r2,r1,#16
00001a 7082 STRB r2,[r0,#2]
;;;122 NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data);
00001c 0e09 LSRS r1,r1,#24
00001e 70c1 STRB r1,[r0,#3]
;;;123 }
000020 4770 BX lr
;;;124
ENDP
000022 0000 DCW 0x0000
|L2.36|
000024 70010000 DCD 0x70010000
|L2.40|
000028 70020000 DCD 0x70020000
AREA ||i.FSMC_NAND_AddressIncrement||, CODE, READONLY, ALIGN=1
FSMC_NAND_AddressIncrement PROC
;;;468
;;;469 Address->Page++;
000000 8882 LDRH r2,[r0,#4]
000002 f44ff44f MOV r1,#0x100
000006 1c52 ADDS r2,r2,#1
000008 b292 UXTH r2,r2
00000a 8082 STRH r2,[r0,#4]
;;;470
;;;471 if(Address->Page == NAND_BLOCK_SIZE)
00000c 2a20 CMP r2,#0x20
00000e d110 BNE |L3.50|
;;;472 {
;;;473 Address->Page = 0;
000010 2300 MOVS r3,#0
000012 8083 STRH r3,[r0,#4]
;;;474 Address->Block++;
000014 8842 LDRH r2,[r0,#2]
000016 1c52 ADDS r2,r2,#1
000018 b292 UXTH r2,r2
00001a 8042 STRH r2,[r0,#2]
;;;475
;;;476 if(Address->Block == NAND_ZONE_SIZE)
00001c f5b2f5b2 CMP r2,#0x400
000020 d107 BNE |L3.50|
;;;477 {
;;;478 Address->Block = 0;
000022 8043 STRH r3,[r0,#2]
;;;479 Address->Zone++;
000024 8802 LDRH r2,[r0,#0]
000026 1c52 ADDS r2,r2,#1
000028 b292 UXTH r2,r2
00002a 8002 STRH r2,[r0,#0]
;;;480
;;;481 if(Address->Zone == NAND_MAX_ZONE)
00002c 2a04 CMP r2,#4
00002e d100 BNE |L3.50|
;;;482 {
;;;483 status = NAND_INVALID_ADDRESS;
000030 0049 LSLS r1,r1,#1
|L3.50|
;;;484 }
;;;485 }
;;;486 }
;;;487
;;;488 return (status);
000032 4608 MOV r0,r1
;;;489 }
000034 4770 BX lr
;;;490
ENDP
AREA ||i.FSMC_NAND_ReadStatus||, CODE, READONLY, ALIGN=2
FSMC_NAND_ReadStatus PROC
000000 2000 MOVS r0,#0
000002 4a06 LDR r2,|L4.28|
000004 2170 MOVS r1,#0x70
000006 7011 STRB r1,[r2,#0]
000008 0609 LSLS r1,r1,#24
00000a 7809 LDRB r1,[r1,#0]
00000c 07ca LSLS r2,r1,#31
00000e d001 BEQ |L4.20|
000010 2001 MOVS r0,#1
|L4.18|
000012 4770 BX lr
|L4.20|
000014 0649 LSLS r1,r1,#25
000016 d5fc BPL |L4.18|
000018 2040 MOVS r0,#0x40
00001a 4770 BX lr
ENDP
|L4.28|
00001c 70010000 DCD 0x70010000
AREA ||i.FSMC_NAND_GetStatus||, CODE, READONLY, ALIGN=1
FSMC_NAND_GetStatus PROC
000000 b500 PUSH {lr}
000002 f04ff04f MOV r3,#0x1000000
000006 f7fff7ff BL FSMC_NAND_ReadStatus
00000a e002 B |L5.18|
|L5.12|
00000c f7fff7ff BL FSMC_NAND_ReadStatus
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