📄 stm32f10x_gpio.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_gpio.o --depend=.\Obj\stm32f10x_gpio.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_gpio.crf ..\..\..\FWLib\library\src\stm32f10x_gpio.c]
THUMB
AREA ||i.GPIO_DeInit||, CODE, READONLY, ALIGN=2
GPIO_DeInit PROC
;;;55
;;;56 switch (*(u32*)&GPIOx)
000000 4a25 LDR r2,|L1.152|
000002 b510 PUSH {r4,lr}
000004 1a81 SUBS r1,r0,r2
000006 1513 ASRS r3,r2,#20
000008 14d4 ASRS r4,r2,#19
00000a 4290 CMP r0,r2
00000c d02e BEQ |L1.108|
00000e dc0d BGT |L1.44|
000010 4922 LDR r1,|L1.156|
000012 1840 ADDS r0,r0,r1
000014 d01c BEQ |L1.80|
000016 4298 CMP r0,r3
000018 d021 BEQ |L1.94|
00001a 42a0 CMP r0,r4
00001c d13b BNE |L1.150|
;;;57 {
;;;58 case GPIOA_BASE:
;;;59 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
;;;60 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
;;;61 break;
;;;62
;;;63 case GPIOB_BASE:
;;;64 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
;;;65 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
;;;66 break;
;;;67
;;;68 case GPIOC_BASE:
;;;69 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
00001e 2101 MOVS r1,#1
000020 2010 MOVS r0,#0x10
000022 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;70 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
000026 2100 MOVS r1,#0
000028 2010 MOVS r0,#0x10
;;;71 break;
00002a e00d B |L1.72|
|L1.44|
00002c 4299 CMP r1,r3 ;56
00002e d024 BEQ |L1.122|
000030 42a1 CMP r1,r4 ;56
000032 d029 BEQ |L1.136|
000034 f5b1f5b1 CMP r1,#0xc00 ;56
000038 d12d BNE |L1.150|
;;;72
;;;73 case GPIOD_BASE:
;;;74 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
;;;75 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
;;;76 break;
;;;77
;;;78 case GPIOE_BASE:
;;;79 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
;;;80 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
;;;81 break;
;;;82
;;;83 case GPIOF_BASE:
;;;84 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
;;;85 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
;;;86 break;
;;;87
;;;88 case GPIOG_BASE:
;;;89 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
00003a 2101 MOVS r1,#1
00003c 020c LSLS r4,r1,#8
00003e 4620 MOV r0,r4
000040 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;90 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
000044 2100 MOVS r1,#0
000046 4620 MOV r0,r4
|L1.72|
000048 e8bde8bd POP {r4,lr}
00004c f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.80|
000050 2101 MOVS r1,#1 ;59
000052 2004 MOVS r0,#4 ;59
000054 f7fff7ff BL RCC_APB2PeriphResetCmd
000058 2100 MOVS r1,#0 ;60
00005a 2004 MOVS r0,#4 ;60
00005c e7f4 B |L1.72|
|L1.94|
00005e 2101 MOVS r1,#1 ;64
000060 2008 MOVS r0,#8 ;64
000062 f7fff7ff BL RCC_APB2PeriphResetCmd
000066 2100 MOVS r1,#0 ;65
000068 2008 MOVS r0,#8 ;65
00006a e7ed B |L1.72|
|L1.108|
00006c 2101 MOVS r1,#1 ;74
00006e 2020 MOVS r0,#0x20 ;74
000070 f7fff7ff BL RCC_APB2PeriphResetCmd
000074 2100 MOVS r1,#0 ;75
000076 2020 MOVS r0,#0x20 ;75
000078 e7e6 B |L1.72|
|L1.122|
00007a 2101 MOVS r1,#1 ;79
00007c 2040 MOVS r0,#0x40 ;79
00007e f7fff7ff BL RCC_APB2PeriphResetCmd
000082 2100 MOVS r1,#0 ;80
000084 2040 MOVS r0,#0x40 ;80
000086 e7df B |L1.72|
|L1.136|
000088 2101 MOVS r1,#1 ;84
00008a 2080 MOVS r0,#0x80 ;84
00008c f7fff7ff BL RCC_APB2PeriphResetCmd
000090 2100 MOVS r1,#0 ;85
000092 2080 MOVS r0,#0x80 ;85
000094 e7d8 B |L1.72|
|L1.150|
;;;91 break;
;;;92
;;;93 default:
;;;94 break;
;;;95 }
;;;96 }
000096 bd10 POP {r4,pc}
;;;97
ENDP
|L1.152|
000098 40011400 DCD 0x40011400
|L1.156|
00009c bffef800 DCD 0xbffef800
AREA ||i.GPIO_AFIODeInit||, CODE, READONLY, ALIGN=1
GPIO_AFIODeInit PROC
;;;107 void GPIO_AFIODeInit(void)
;;;108 {
000000 b510 PUSH {r4,lr}
;;;109 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
000002 2101 MOVS r1,#1
000004 4608 MOV r0,r1
000006 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;110 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
00000a 2100 MOVS r1,#0
00000c e8bde8bd POP {r4,lr}
000010 2001 MOVS r0,#1
000012 f7fff7ff B.W RCC_APB2PeriphResetCmd
;;;111 }
;;;112
ENDP
AREA ||i.GPIO_Init||, CODE, READONLY, ALIGN=2
GPIO_Init PROC
;;;124 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
;;;125 {
000000 b5f0 PUSH {r4-r7,lr}
;;;126 u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
;;;127 u32 tmpreg = 0x00, pinmask = 0x00;
;;;128
;;;129 /* Check the parameters */
;;;130 assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
;;;131 assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
;;;132 assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
;;;133
;;;134 /*---------------------------- GPIO Mode Configuration -----------------------*/
;;;135 currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
000002 78cb LDRB r3,[r1,#3]
000004 2200 MOVS r2,#0 ;126
;;;136
;;;137 if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
000006 06dc LSLS r4,r3,#27
000008 f003f003 AND r3,r3,#0xf ;135
00000c d501 BPL |L3.18|
;;;138 {
;;;139 /* Check the parameters */
;;;140 assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
;;;141 /* Output mode */
;;;142 currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
00000e 788c LDRB r4,[r1,#2]
000010 4323 ORRS r3,r3,r4
|L3.18|
;;;143 }
;;;144
;;;145 /*---------------------------- GPIO CRL Configuration ------------------------*/
;;;146 /* Configure the eight low port pins */
;;;147 if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
000012 880c LDRH r4,[r1,#0]
000014 270f MOVS r7,#0xf
000016 f014f014 TST r4,#0xff
00001a f04ff04f MOV r12,#1
00001e d01c BEQ |L3.90|
;;;148 {
;;;149 tmpreg = GPIOx->CRL;
000020 f8d0f8d0 LDR.W r5,[r0,#0]
|L3.36|
;;;150
;;;151 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
;;;152 {
;;;153 pos = ((u32)0x01) << pinpos;
;;;154 /* Get the port pins position */
;;;155 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
000024 880e LDRH r6,[r1,#0]
000026 fa0cfa0c LSL r4,r12,r2 ;153
00002a 4026 ANDS r6,r6,r4
;;;156
;;;157 if (currentpin == pos)
00002c 42a6 CMP r6,r4
00002e d110 BNE |L3.82|
000030 0096 LSLS r6,r2,#2
;;;158 {
;;;159 pos = pinpos << 2;
;;;160 /* Clear the corresponding low control register bits */
;;;161 pinmask = ((u32)0x0F) << pos;
000032 fa07fa07 LSL lr,r7,r6
;;;162 tmpreg &= ~pinmask;
000036 ea25ea25 BIC lr,r5,lr
;;;163
;;;164 /* Write the mode configuration in the corresponding bits */
;;;165 tmpreg |= (currentmode << pos);
00003a fa03fa03 LSL r5,r3,r6
;;;166
;;;167 /* Reset the corresponding ODR bit */
;;;168 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
00003e 78ce LDRB r6,[r1,#3]
000040 ea45ea45 ORR r5,r5,lr ;165
000044 2e28 CMP r6,#0x28
000046 d100 BNE |L3.74|
;;;169 {
;;;170 GPIOx->BRR = (((u32)0x01) << pinpos);
000048 6144 STR r4,[r0,#0x14]
|L3.74|
;;;171 }
;;;172 /* Set the corresponding ODR bit */
;;;173 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
00004a 78ce LDRB r6,[r1,#3]
00004c 2e48 CMP r6,#0x48
00004e d100 BNE |L3.82|
;;;174 {
;;;175 GPIOx->BSRR = (((u32)0x01) << pinpos);
000050 6104 STR r4,[r0,#0x10]
|L3.82|
000052 1c52 ADDS r2,r2,#1 ;151
000054 2a08 CMP r2,#8 ;151
000056 d3e5 BCC |L3.36|
;;;176 }
;;;177 }
;;;178 }
;;;179 GPIOx->CRL = tmpreg;
000058 6005 STR r5,[r0,#0]
|L3.90|
;;;180 }
;;;181
;;;182 /*---------------------------- GPIO CRH Configuration ------------------------*/
;;;183 /* Configure the eight high port pins */
;;;184 if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
00005a 880a LDRH r2,[r1,#0]
00005c 2aff CMP r2,#0xff
00005e d91e BLS |L3.158|
;;;185 {
;;;186 tmpreg = GPIOx->CRH;
000060 6845 LDR r5,[r0,#4]
;;;187 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
000062 2200 MOVS r2,#0
|L3.100|
;;;188 {
;;;189 pos = (((u32)0x01) << (pinpos + 0x08));
000064 f102f102 ADD r6,r2,#8
000068 fa0cfa0c LSL r4,r12,r6
;;;190 /* Get the port pins position */
;;;191 currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
00006c 880e LDRH r6,[r1,#0]
00006e 4026 ANDS r6,r6,r4
;;;192 if (currentpin == pos)
000070 42a6 CMP r6,r4
000072 d110 BNE |L3.150|
000074 0096 LSLS r6,r2,#2
;;;193 {
;;;194 pos = pinpos << 2;
;;;195 /* Clear the corresponding high control register bits */
;;;196 pinmask = ((u32)0x0F) << pos;
000076 fa07fa07 LSL lr,r7,r6
;;;197 tmpreg &= ~pinmask;
00007a ea25ea25 BIC lr,r5,lr
;;;198
;;;199 /* Write the mode configuration in the corresponding bits */
;;;200 tmpreg |= (currentmode << pos);
00007e fa03fa03 LSL r5,r3,r6
;;;201
;;;202 /* Reset the corresponding ODR bit */
;;;203 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
000082 78ce LDRB r6,[r1,#3]
000084 ea45ea45 ORR r5,r5,lr ;200
000088 2e28 CMP r6,#0x28
00008a d100 BNE |L3.142|
;;;204 {
;;;205 GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
00008c 6144 STR r4,[r0,#0x14]
|L3.142|
;;;206 }
;;;207 /* Set the corresponding ODR bit */
;;;208 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
00008e 78ce LDRB r6,[r1,#3]
000090 2e48 CMP r6,#0x48
000092 d100 BNE |L3.150|
;;;209 {
;;;210 GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
000094 6104 STR r4,[r0,#0x10]
|L3.150|
000096 1c52 ADDS r2,r2,#1 ;187
000098 2a08 CMP r2,#8 ;187
00009a d3e3 BCC |L3.100|
;;;211 }
;;;212 }
;;;213 }
;;;214 GPIOx->CRH = tmpreg;
00009c 6045 STR r5,[r0,#4]
|L3.158|
;;;215 }
;;;216 }
00009e bdf0 POP {r4-r7,pc}
;;;217
ENDP
AREA ||i.GPIO_StructInit||, CODE, READONLY, ALIGN=1
GPIO_StructInit PROC
;;;228 /* Reset GPIO init structure parameters values */
;;;229 GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
000000 f64ff64f MOV r1,#0xffff
000004 8001 STRH r1,[r0,#0]
;;;230 GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
000006 2102 MOVS r1,#2
000008 7081 STRB r1,[r0,#2]
;;;231 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
00000a 2104 MOVS r1,#4
00000c 70c1 STRB r1,[r0,#3]
;;;232 }
00000e 4770 BX lr
;;;233
ENDP
AREA ||i.GPIO_ReadInputDataBit||, CODE, READONLY, ALIGN=1
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