📄 stm32f10x_sdio.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_sdio.o --depend=.\Obj\stm32f10x_sdio.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_sdio.crf ..\..\..\FWLib\library\src\stm32f10x_sdio.c]
THUMB
AREA ||i.SDIO_DeInit||, CODE, READONLY, ALIGN=2
SDIO_DeInit PROC
;;;106 {
;;;107 SDIO->POWER = 0x00000000;
000000 4806 LDR r0,|L1.28|
000002 2100 MOVS r1,#0
000004 6001 STR r1,[r0,#0]
;;;108 SDIO->CLKCR = 0x00000000;
000006 6041 STR r1,[r0,#4]
;;;109 SDIO->ARG = 0x00000000;
000008 6081 STR r1,[r0,#8]
;;;110 SDIO->CMD = 0x00000000;
00000a 60c1 STR r1,[r0,#0xc]
;;;111 SDIO->DTIMER = 0x00000000;
00000c 6241 STR r1,[r0,#0x24]
;;;112 SDIO->DLEN = 0x00000000;
00000e 6281 STR r1,[r0,#0x28]
;;;113 SDIO->DCTRL = 0x00000000;
000010 62c1 STR r1,[r0,#0x2c]
;;;114 SDIO->ICR = 0x00C007FF;
000012 4a03 LDR r2,|L1.32|
000014 6382 STR r2,[r0,#0x38]
;;;115 SDIO->MASK = 0x00000000;
000016 63c1 STR r1,[r0,#0x3c]
;;;116 }
000018 4770 BX lr
;;;117
ENDP
00001a 0000 DCW 0x0000
|L1.28|
00001c 40018000 DCD 0x40018000
|L1.32|
000020 00c007ff DCD 0x00c007ff
AREA ||i.SDIO_Init||, CODE, READONLY, ALIGN=2
SDIO_Init PROC
;;;128 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
;;;129 {
000000 b570 PUSH {r4-r6,lr}
;;;130 u32 tmpreg = 0;
;;;131
;;;132 /* Check the parameters */
;;;133 assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
;;;134 assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
;;;135 assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
;;;136 assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
;;;137 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
;;;138
;;;139 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
;;;140 /* Get the SDIO CLKCR value */
;;;141 tmpreg = SDIO->CLKCR;
000002 4b09 LDR r3,|L2.40|
000004 6859 LDR r1,[r3,#4]
;;;142
;;;143 /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
;;;144 tmpreg &= CLKCR_CLEAR_MASK;
000006 f647f647 MOV r2,#0x7eff
00000a 4391 BICS r1,r1,r2
;;;145
;;;146 /* Set CLKDIV bits according to SDIO_ClockDiv value */
;;;147 /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
;;;148 /* Set BYPASS bit according to SDIO_ClockBypass value */
;;;149 /* Set WIDBUS bits according to SDIO_BusWide value */
;;;150 /* Set NEGEDGE bits according to SDIO_ClockEdge value */
;;;151 /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
;;;152 tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
00000c e9d0e9d0 LDRD r6,r5,[r0,#0xc]
000010 7802 LDRB r2,[r0,#0]
000012 4332 ORRS r2,r2,r6
000014 e9d0e9d0 LDRD r6,r4,[r0,#4]
000018 432c ORRS r4,r4,r5
00001a 4322 ORRS r2,r2,r4
00001c 6940 LDR r0,[r0,#0x14]
00001e 4332 ORRS r2,r2,r6
000020 4302 ORRS r2,r2,r0
000022 430a ORRS r2,r2,r1
;;;153 SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
;;;154 SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
;;;155
;;;156 /* Write to SDIO CLKCR */
;;;157 SDIO->CLKCR = tmpreg;
000024 605a STR r2,[r3,#4]
;;;158 }
000026 bd70 POP {r4-r6,pc}
;;;159
ENDP
|L2.40|
000028 40018000 DCD 0x40018000
AREA ||i.SDIO_StructInit||, CODE, READONLY, ALIGN=1
SDIO_StructInit PROC
;;;170 /* SDIO_InitStruct members default value */
;;;171 SDIO_InitStruct->SDIO_ClockDiv = 0x00;
000000 2100 MOVS r1,#0
000002 7001 STRB r1,[r0,#0]
;;;172 SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
;;;173 SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
000004 6041 STR r1,[r0,#4]
;;;174 SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
000006 6081 STR r1,[r0,#8]
;;;175 SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
000008 60c1 STR r1,[r0,#0xc]
;;;176 SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
00000a 6101 STR r1,[r0,#0x10]
;;;177 }
00000c 6141 STR r1,[r0,#0x14]
00000e 4770 BX lr
;;;178
ENDP
AREA ||i.SDIO_ClockCmd||, CODE, READONLY, ALIGN=2
SDIO_ClockCmd PROC
;;;187 void SDIO_ClockCmd(FunctionalState NewState)
;;;188 {
000000 4901 LDR r1,|L4.8|
;;;189 /* Check the parameters */
;;;190 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;191
;;;192 *(vu32 *) CLKCR_CLKEN_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;193 }
000004 4770 BX lr
;;;194
ENDP
000006 0000 DCW 0x0000
|L4.8|
000008 423000a0 DCD 0x423000a0
AREA ||i.SDIO_SetPowerState||, CODE, READONLY, ALIGN=2
SDIO_SetPowerState PROC
;;;209
;;;210 SDIO->POWER &= PWR_PWRCTRL_MASK;
000000 4904 LDR r1,|L5.20|
000002 680a LDR r2,[r1,#0]
000004 f022f022 BIC r2,r2,#3
000008 600a STR r2,[r1,#0]
;;;211 SDIO->POWER |= SDIO_PowerState;
00000a 680a LDR r2,[r1,#0]
00000c 4302 ORRS r2,r2,r0
00000e 600a STR r2,[r1,#0]
;;;212 }
000010 4770 BX lr
;;;213
ENDP
000012 0000 DCW 0x0000
|L5.20|
000014 40018000 DCD 0x40018000
AREA ||i.SDIO_GetPowerState||, CODE, READONLY, ALIGN=2
SDIO_GetPowerState PROC
;;;226 {
;;;227 return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
000000 4802 LDR r0,|L6.12|
000002 6800 LDR r0,[r0,#0]
000004 f000f000 AND r0,r0,#3
;;;228 }
000008 4770 BX lr
;;;229
ENDP
00000a 0000 DCW 0x0000
|L6.12|
00000c 40018000 DCD 0x40018000
AREA ||i.SDIO_ITConfig||, CODE, READONLY, ALIGN=2
SDIO_ITConfig PROC
;;;274 void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState)
;;;275 {
000000 4a04 LDR r2,|L7.20|
;;;276 /* Check the parameters */
;;;277 assert_param(IS_SDIO_IT(SDIO_IT));
;;;278 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;279
;;;280 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;281 {
;;;282 /* Enable the SDIO interrupts */
;;;283 SDIO->MASK |= SDIO_IT;
000004 6bd1 LDR r1,[r2,#0x3c]
000006 d001 BEQ |L7.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L7.14|
|L7.12|
;;;284 }
;;;285 else
;;;286 {
;;;287 /* Disable the SDIO interrupts */
;;;288 SDIO->MASK &= ~SDIO_IT;
00000c 4381 BICS r1,r1,r0
|L7.14|
00000e 63d1 STR r1,[r2,#0x3c] ;283
;;;289 }
;;;290 }
000010 4770 BX lr
;;;291
ENDP
000012 0000 DCW 0x0000
|L7.20|
000014 40018000 DCD 0x40018000
AREA ||i.SDIO_DMACmd||, CODE, READONLY, ALIGN=2
SDIO_DMACmd PROC
;;;300 void SDIO_DMACmd(FunctionalState NewState)
;;;301 {
000000 4901 LDR r1,|L8.8|
;;;302 /* Check the parameters */
;;;303 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;304
;;;305 *(vu32 *) DCTRL_DMAEN_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;306 }
000004 4770 BX lr
;;;307
ENDP
000006 0000 DCW 0x0000
|L8.8|
000008 4230058c DCD 0x4230058c
AREA ||i.SDIO_SendCommand||, CODE, READONLY, ALIGN=2
SDIO_SendCommand PROC
;;;318 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
;;;319 {
000000 b530 PUSH {r4,r5,lr}
;;;320 u32 tmpreg = 0;
;;;321
;;;322 /* Check the parameters */
;;;323 assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
;;;324 assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
;;;325 assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
;;;326 assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
;;;327
;;;328 /*---------------------------- SDIO ARG Configuration ------------------------*/
;;;329 /* Set the SDIO Argument value */
;;;330 SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
000002 4908 LDR r1,|L9.36|
000004 6802 LDR r2,[r0,#0]
000006 608a STR r2,[r1,#8]
;;;331
;;;332 /*---------------------------- SDIO CMD Configuration ------------------------*/
;;;333 /* Get the SDIO CMD value */
;;;334 tmpreg = SDIO->CMD;
000008 68ca LDR r2,[r1,#0xc]
;;;335
;;;336 /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
;;;337 tmpreg &= CMD_CLEAR_MASK;
;;;338 /* Set CMDINDEX bits according to SDIO_CmdIndex value */
;;;339 /* Set WAITRESP bits according to SDIO_Response value */
;;;340 /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
;;;341 /* Set CPSMEN bits according to SDIO_CPSM value */
;;;342 tmpreg |= (u32)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
00000a e9d0e9d0 LDRD r5,r4,[r0,#8]
00000e 6843 LDR r3,[r0,#4]
000010 6900 LDR r0,[r0,#0x10]
000012 432b ORRS r3,r3,r5
000014 4304 ORRS r4,r4,r0
000016 f36ff36f BFC r2,#0,#11 ;337
00001a 4323 ORRS r3,r3,r4
00001c 4313 ORRS r3,r3,r2
;;;343 | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
;;;344
;;;345 /* Write to SDIO CMD */
;;;346 SDIO->CMD = tmpreg;
00001e 60cb STR r3,[r1,#0xc]
;;;347 }
000020 bd30 POP {r4,r5,pc}
;;;348
ENDP
000022 0000 DCW 0x0000
|L9.36|
000024 40018000 DCD 0x40018000
AREA ||i.SDIO_CmdStructInit||, CODE, READONLY, ALIGN=1
SDIO_CmdStructInit PROC
;;;359 /* SDIO_CmdInitStruct members default value */
;;;360 SDIO_CmdInitStruct->SDIO_Argument = 0x00;
000000 2100 MOVS r1,#0
;;;361 SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
000002 6001 STR r1,[r0,#0]
;;;362 SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
000004 6041 STR r1,[r0,#4]
;;;363 SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
000006 6081 STR r1,[r0,#8]
;;;364 SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
000008 60c1 STR r1,[r0,#0xc]
;;;365 }
00000a 6101 STR r1,[r0,#0x10]
00000c 4770 BX lr
;;;366
ENDP
AREA ||i.SDIO_GetCommandResponse||, CODE, READONLY, ALIGN=2
SDIO_GetCommandResponse PROC
;;;376 {
;;;377 return (u8)(SDIO->RESPCMD);
000000 4801 LDR r0,|L11.8|
000002 6900 LDR r0,[r0,#0x10]
000004 b2c0 UXTB r0,r0
;;;378 }
000006 4770 BX lr
;;;379
ENDP
|L11.8|
000008 40018000 DCD 0x40018000
AREA ||i.SDIO_GetResponse||, CODE, READONLY, ALIGN=2
SDIO_GetResponse PROC
;;;396
;;;397 return (*(vu32 *)(SDIO_RESP_ADDR + SDIO_RESP));
000000 4901 LDR r1,|L12.8|
000002 4408 ADD r0,r0,r1
000004 6940 LDR r0,[r0,#0x14]
;;;398 }
000006 4770 BX lr
;;;399
ENDP
|L12.8|
000008 40018000 DCD 0x40018000
AREA ||i.SDIO_DataConfig||, CODE, READONLY, ALIGN=2
SDIO_DataConfig PROC
;;;410 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
;;;411 {
000000 b530 PUSH {r4,r5,lr}
;;;412 u32 tmpreg = 0;
;;;413
;;;414 /* Check the parameters */
;;;415 assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
;;;416 assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
;;;417 assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
;;;418 assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
;;;419 assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
;;;420
;;;421 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
;;;422 /* Set the SDIO Data TimeOut value */
;;;423 SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
000002 4909 LDR r1,|L13.40|
000004 6802 LDR r2,[r0,#0]
000006 624a STR r2,[r1,#0x24]
;;;424
;;;425 /*---------------------------- SDIO DLEN Configuration -----------------------*/
;;;426 /* Set the SDIO DataLength value */
;;;427 SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
000008 6842 LDR r2,[r0,#4]
00000a 628a STR r2,[r1,#0x28]
;;;428
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