m32r.md

linux下的gcc编译器

	(lt:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:SI 17))]
  ""
  [(set (reg:SI 17)
	(lt:SI (match_dup 1)
	       (match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))]
  "")

(define_expand "sle"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (GET_CODE (op2) == CONST_INT)
    {
      HOST_WIDE_INT value = INTVAL (op2);
      if (value >= 2147483647)
	{
	  emit_move_insn (op0, GEN_INT (1));
	  DONE;
	}

      op2 = GEN_INT (value+1);
      if (value < -32768 || value >= 32767)
	op2 = force_reg (mode, op2);

      emit_insn (gen_slt_insn (op0, op1, op2));
      DONE;
    }

  if (! register_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sle_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sle_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(le:SI (match_operand:SI 1 "register_operand" "r")
	       (match_operand:SI 2 "register_operand" "r")))
   (clobber (reg:SI 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(le:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "register_operand" "")))
   (clobber (reg:SI 17))]
  "!optimize_size"
  [(set (reg:SI 17)
	(lt:SI (match_dup 2)
	       (match_dup 1)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(le:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "register_operand" "")))
   (clobber (reg:SI 17))]
  "optimize_size"
  [(set (reg:SI 17)
	(lt:SI (match_dup 2)
	       (match_dup 1)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_expand "sgt"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! register_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_slt_insn (op0, op2, op1));
  DONE;
}")

(define_expand "sge"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! reg_or_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sge_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sge_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(ge:SI (match_operand:SI 1 "register_operand" "r,r")
	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
   (clobber (reg:SI 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8,10")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(ge:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:SI 17))]
  "!optimize_size"
  [(set (reg:SI 17)
	(lt:SI (match_dup 1)
	       (match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(ge:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:SI 17))]
  "optimize_size"
  [(set (reg:SI 17)
	(lt:SI (match_dup 1)
	       (match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_expand "sltu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! reg_or_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sltu_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sltu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
   (clobber (reg:SI 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "6,8")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(ltu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:SI 17))]
  ""
  [(set (reg:SI 17)
	(ltu:SI (match_dup 1)
		(match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))]
  "")

(define_expand "sleu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (GET_CODE (op2) == CONST_INT)
    {
      HOST_WIDE_INT value = INTVAL (op2);
      if (value >= 2147483647)
	{
	  emit_move_insn (op0, GEN_INT (1));
	  DONE;
	}

      op2 = GEN_INT (value+1);
      if (value < 0 || value >= 32767)
	op2 = force_reg (mode, op2);

      emit_insn (gen_sltu_insn (op0, op1, op2));
      DONE;
    }

  if (! register_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sleu_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sleu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(leu:SI (match_operand:SI 1 "register_operand" "r")
		(match_operand:SI 2 "register_operand" "r")))
   (clobber (reg:SI 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(leu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "register_operand" "")))
   (clobber (reg:SI 17))]
  "!optimize_size"
  [(set (reg:SI 17)
	(ltu:SI (match_dup 2)
		(match_dup 1)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(leu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "register_operand" "")))
   (clobber (reg:SI 17))]
  "optimize_size"
  [(set (reg:SI 17)
	(ltu:SI (match_dup 2)
		(match_dup 1)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_expand "sgtu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! register_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sltu_insn (op0, op2, op1));
  DONE;
}")

(define_expand "sgeu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! reg_or_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sgeu_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sgeu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(geu:SI (match_operand:SI 1 "register_operand" "r,r")
		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
   (clobber (reg:SI 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8,10")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(geu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:SI 17))]
  "!optimize_size"
  [(set (reg:SI 17)
	(ltu:SI (match_dup 1)
		(match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(geu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:SI 17))]
  "optimize_size"
  [(set (reg:SI 17)
	(ltu:SI (match_dup 1)
		(match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_insn "movcc_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(reg:SI 17))]
  ""
  "mvfc %0, cbr"
  [(set_attr "type" "misc")
   (set_attr "length" "2")])


;; Unconditional and other jump instructions.

(define_insn "jump"
  [(set (pc) (label_ref (match_operand 0 "" "")))]
  ""
  "bra %l0"
  [(set_attr "type" "uncond_branch")
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 400))
					   (const_int 800))
				      (const_int 2)
				      (const_int 4)))])

(define_insn "indirect_jump"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
  ""
  "jmp %a0"
  [(set_attr "type" "uncond_branch")
   (set_attr "length" "2")])

(define_insn "return"
  [(return)]
  "direct_return ()"
  "jmp lr"
  [(set_attr "type" "uncond_branch")
   (set_attr "length" "2")])
 
(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jmp %a0"
  [(set_attr "type" "uncond_branch")
   (set_attr "length" "2")])

(define_expand "call"
  ;; operands[1] is stack_size_rtx
  ;; operands[2] is next_arg_register
  [(parallel [(call (match_opera