dsp16xx.md

linux下的gcc编译器

		case 6:
		case 7:
		   return \"%u0=%u1\;%w0=%w1\";
		case 8:
		case 9:
		   return \"\";
                default:
                  abort();
        }
}"
[(set_attr "type" "special,data_move_multiple,f3_alu,data_move_multiple,data_move_multiple,data_move_multiple,data_move_multiple,data_move_multiple,nothing,nothing")])


;; NOTE: It is cheaper to do 'y = *r0', than 'r0 = *r0'.

(define_expand "movqi"
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, QImode))
    DONE;
}")

;; The movqi pattern with the parallel is used for addqi insns (which have a parallel)
;; that are turned into moveqi insns by the flow phase. This happens when an auto-increment
;; is detected.

(define_insn "match_movqi1"
  [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>")
		   (match_operand:QI 1 "general_operand"       "r,A,J,i,m<>,D,Y,e,0,m<>,xyz"))
	      (clobber (match_scratch:QI 2 "=X,X,X,X,X,X,X,X,X,X,X"))])]
  "register_operand(operands[0], QImode)
   || register_operand(operands[1], QImode)"
  "*
{
	switch (which_alternative)
	{
		case 0:
		   /* We have to use the move mneumonic otherwise the 1610 will
		      attempt to transfer all 32-bits of 'y', 'p' or an accumulator
		      , which we don't want */
		   if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
			|| IS_ACCUM_REG(REGNO(operands[1])))
		       return \"move %0=%1\";
		   else
		       return \"%0=%1\";

		case 1:
 		   return \"%0=%1\";

		case 2:
		   return \"set %0=%H1\";

		case 3:
                   return \"%0=%H1\";

		case 4:
		   return \"%0=%1\";

		case 5:
		case 6:
                   return \"%0=%1\";

		case 7:
		   return \"%0=%1\";

		case 8:
		   return \"\";

                case 9: case 10:
		   return \"%0=%1\";
                default:
                  abort();
	}
}"
[(set_attr "type" "data_move,data_move,data_move_short_i,data_move_i,data_move_memory,data_move_memory,data_move_memory,data_move_memory,nothing,malu,malu")])

(define_insn "match_movqi2"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>")
	(match_operand:QI 1 "general_operand"       "r,A,J,i,m<>,D,Y,e,0,m<>,xyz"))]
  "register_operand(operands[0], QImode)
   || register_operand(operands[1], QImode)"
  "*
{
	switch (which_alternative)
	{
		case 0:
		   /* We have to use the move mneumonic otherwise the 1610 will
		      attempt to transfer all 32-bits of 'y', 'p' or an accumulator
		      , which we don't want */
		   if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
			|| IS_ACCUM_REG(REGNO(operands[1])))
		       return \"move %0=%1\";
		   else
		       return \"%0=%1\";

		case 1:
 		   return \"%0=%1\";

		case 2:
		   return \"set %0=%H1\";

		case 3:
                   return \"%0=%H1\";

		case 4:
		   return \"%0=%1\";

		case 5:
		case 6:
                   return \"%0=%1\";

		case 7:
		   return \"%0=%1\";

		case 8:
		   return \"\";

                case 9: case 10:
		   return \"%0=%1\";
                default:
                  abort();
	}
}"
[(set_attr "type" "data_move,data_move,data_move_short_i,data_move_i,data_move_memory,data_move_memory,data_move_memory,data_move_memory,nothing,malu,malu")])

(define_expand "reload_inqi"
  [(set (match_operand:QI 0 "register_operand" "=u")
        (match_operand:QI 1 "sp_operand" ""))
   (clobber (match_operand:QI 2 "register_operand" "=&q"))]
  ""
  "
{
  rtx addr_reg = XEXP (operands[1], 0);
  rtx offset = XEXP (operands[1], 1);

  /* First, move the frame or stack pointer to the accumulator */
  emit_move_insn (operands[0], addr_reg);

  /* Then generate the add insn */
  emit_insn (gen_rtx_PARALLEL
	     (VOIDmode, 
	      gen_rtvec (2,
			 gen_rtx_SET (VOIDmode, operands[0], 
				      gen_rtx_PLUS (QImode, operands[0],
						    offset)),
			 gen_rtx_CLOBBER (VOIDmode, operands[2]))));
  DONE;
}")

(define_expand "reload_inhi"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (match_operand:HI 1 "register_operand" "r"))
   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
  ""
  "
{
  /* Check for an overlap of operand 2 (an accumulator) with
     the msw of operand 0. If we have an overlap we must reverse
     the order of the moves.  */

  if (REGNO(operands[2]) == REGNO(operands[0]))
    {
      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode));
      emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]);
      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode));
      emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]);
    }
  else
    {
      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode));
      emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]);
      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode));
      emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]);
    }

  DONE;
}")


(define_expand "reload_outhi"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (match_operand:HI 1 "register_operand" "r"))
   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
  ""
  "
{
	emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode));
	emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]);
	emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode));
	emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]);
	DONE;
}")

(define_expand "movstrqi"
  [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
		   (match_operand:BLK 1 "memory_operand" ""))
	      (use (match_operand:QI 2 "const_int_operand" ""))
	      (use (match_operand:QI 3 "const_int_operand" ""))
	      (clobber (match_scratch:QI 4 ""))
	      (clobber (match_dup 5))
	      (clobber (match_dup 6))])]
  ""
  "
{
  rtx addr0, addr1;

  if (GET_CODE (operands[2]) != CONST_INT)
    FAIL;

  if (INTVAL(operands[2]) > 127)
    FAIL;

  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
  addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));

  operands[5] = addr0;
  operands[6] = addr1;

  operands[0] = change_address (operands[0], VOIDmode, addr0);
  operands[1] = change_address (operands[1], VOIDmode, addr1);
}")

(define_insn ""
  [(set (mem:BLK (match_operand:QI 0 "register_operand" "a"))
	(mem:BLK (match_operand:QI 1 "register_operand" "a")))
   (use (match_operand:QI 2 "const_int_operand" "n"))
   (use (match_operand:QI 3 "immediate_operand" "i"))
   (clobber (match_scratch:QI 4 "=x"))
   (clobber (match_dup 0))
   (clobber (match_dup 1))]
  ""
  "*
{ return output_block_move (operands); }")


;; Floating point move insns


(define_expand "movhf"
  [(set (match_operand:HF 0 "general_operand" "")
	(match_operand:HF 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, HFmode))
    DONE;
}")

(define_insn "match_movhf"
  [(set (match_operand:HF 0 "nonimmediate_operand" "=A,Z,d,d,m,d,Y")
	(match_operand:HF 1 "general_operand"       "d,A,F,m,d,Y,d"))]
  ""
  "*
{
	/* NOTE: When loading the register 16 bits at a time we
	   MUST load the high half FIRST (because the 1610 zeros
	   the low half) and then load the low half */

	switch (which_alternative)
        {
		/* register to accumulator */
		case 0:
 		   return \"%0=%1\";
		case 1:
		   return \"%u0=%u1\;%w0=%w1\";
		case 2:
		   output_dsp16xx_float_const(operands);
		   return \"\";
		case 3:
		   double_reg_from_memory(operands);
		   return \"\";
		case 4:
		   double_reg_to_memory(operands);
		   return \"\";
		case 5:
		case 6:
		   return \"%u0=%u1\;%w0=%w1\";
                default:
                  abort();
        }
}"
[(set_attr "type" "move,move,load_i,load,store,load,store")])



(define_expand "reload_inhf"
  [(set (match_operand:HF 0 "register_operand" "=r")
        (match_operand:HF 1 "register_operand" "r"))
   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
  ""
  "
{
  /* Check for an overlap of operand 2 (an accumulator) with
     the msw of operand 0. If we have an overlap we must reverse
     the order of the moves.  */

  if (REGNO(operands[2]) == REGNO(operands[0]))
    {
      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode));
      emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]);
      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode));
      emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]);
    }
  else
    {
      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode));
      emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]);
      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode));
      emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]);
    }
  
  DONE;
}")

(define_expand "reload_outhf"
  [(set (match_operand:HF 0 "register_operand" "=r")
        (match_operand:HF 1 "register_operand" "r"))
   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
  ""
  "
{
	emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode));
	emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]);
	emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode));
	emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]);
	DONE;
}")


;;
;; CONVERSION INSTRUCTIONS
;;

(define_expand "extendqihi2"
  [(clobber (match_dup 2))
   (set (match_dup 3) (match_operand:QI 1 "register_operand" ""))
   (set (match_operand:HI 0 "register_operand" "")
	(ashift:HI (match_dup 2)
		   (const_int 16)))
   (set (match_dup 0)
	(ashiftrt:HI (match_dup 0) (const_int 16)))]
  ""
  "
{
	operands[2] = gen_reg_rtx (HImode);
	operands[3] = gen_rtx_SUBREG (QImode, operands[2], 1);
}")

(define_insn "internal_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=A")
	(sign_extend:HI (match_operand:QI 1 "register_operand" "ku")))]
  "TARGET_BMU"
  "%0 = extracts(%m1, 0x1000)"
[(set_attr "type" "shift_i")])

;;(define_insn "extendqihi2"
;;  [(set (match_operand:HI 0 "register_operand" "=A")
;;        (sign_extend:HI (match_operand:QI 1 "register_operand" "h")))]
;;  ""
;;  "%0 = %1 >> 16")

;;(define_insn "zero_extendqihi2"
;;  [(set (match_operand:HI 0 "register_operand" "=t,f,A,?d,?A")
;;        (zero_extend:HI (match_operand:QI 1 "register_operand" "w,z,ku,A,r")))]
;;  ""
;;  "*
;; {
;;  switch (which_alternative)
;;    {
;;    case 0:
;;    case 1:
;;      return \"%0=0\";
;;
;;    case 2:
;;      if (REGNO(operands[1]) == (REGNO(operands[0]) + 1))
;;        return \"%0=0\";
;;      else
;;	return \"%w0=%1\;%0=0\";
;;    case 3:
;;      return \"%w0=%1\;%0=0\";
;;
;;    case 4:
;;      if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
;;	  || IS_ACCUM_REG(REGNO(operands[1])))
;;	return \"move %w0=%1\;%0=0\";
;;      else
;;	return \"%w0=%1\;%0=0\";
;;    default:
;;      abort();
;;    }
;; }")

;;(define_expand "zero_extendqihi2"
;;  [(clobber (match_dup 2))
;;   (set (match_dup 3) (match_operand:QI 1 "register_operand" ""))
;;   (set (match_operand:HI 0 "register_operand" "")
;;	(ashift:HI (match_dup 2)
;;		   (const_int 16)))
;;   (set (match_dup 0)
;;	(lshiftrt:HI (match_dup 0) (const_int 16)))]
;;  ""
;;  "
;;{
;;	operands[2] = gen_reg_rtx (HImode);
;;	operands[3] = gen_rtx (SUBREG, QImode, operands[2], 1);
;;}")

(define_expand "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "")
      (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
  ""
  "")  
	

(define_insn "match_zero_extendqihi_bmu"
  [(set (match_operand:HI 0 "register_operand" "=?*Z,?*Z,?A,A")
        (zero_extend:HI (match_operand:QI 1 "register_operand" "?A,?*Y,*Z*x*a*W*Y,ku")))]
  "TARGET_BMU"
  "*
 {
    switch (which_alternative)
      {
        case 0:
          return \"%w0=%1\;%0=0\";

        case 1:
          return \"%w0=%1\;%0=0\";

        case 2:
          if (REGNO(operands[1]) == (REGNO(operands[0]) + 1))
            return \"%0=0\";
          else if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
	           || IS_ACCUM_REG(REGNO(operands[1])))
          {
            return \"move %w0=%1\;%0=0\";
          }
          else
            return \"%w0=%1\;%0=0\";

	case 3:
	  return \"%0 = extractz(%m1, 0x1000)\";
        default:
          abort();
      }
  }"
  [(set_attr "type" "data_move_2,data_move_2,data_move_2,shift_i")])

(define_insn "match_zero_extendqihi2_nobmu"
  [(set (match_operand:HI 0 "register_operand" "=?Z,?Z,A")
        (zero_extend:HI (match_operand:QI 1 "register_operand" "A,Y,r")))]
  ""
  "*
 {
    switch (which_alternative)
      {
        case 0:
          return \"%w0=%1\;%0=0\";

        case 1:
          return \"%w0=%1\;%0=0\";

        case 2:
          if (REGNO(operands[1]) + 1 == (REGNO(operands[0]) + 1))
            return \"%0=0\";
          else if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
	           || IS_ACCUM_REG(REGNO(operands[1])))
          {
            return \"move %w0=%1\;%0=0\";