cris.md

linux下的gcc编译器

  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
	(match_operator:QI
	 5 "cris_commutative_orth_op"
	 [(mem:QI
	   (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
		    (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
	  (match_operand:QI 1 "register_operand" "0,0,0")]))
   (set (match_operand:SI 4 "register_operand" "=*2,r,r")
	(plus:SI (match_dup 2)
		 (match_dup 3)))]
  "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
  "*
{
  if (which_alternative == 0
      && (GET_CODE (operands[3]) != CONST_INT
	  || INTVAL (operands[3]) > 127
	  || INTVAL (operands[3]) < -128
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
    return \"#\";
  return \"%x5.%s0 [%4=%2%S3],%0\";
}")

;; HImode

(define_insn "*op_swap_sidehi"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
	(match_operator:HI
	 5 "cris_commutative_orth_op"
	 [(mem:HI
	   (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
		    (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
	  (match_operand:HI 1 "register_operand" "0,0,0")]))
   (set (match_operand:SI 4 "register_operand" "=*2,r,r")
	(plus:SI (match_dup 2)
		 (match_dup 3)))]
  "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
  "*
{
  if (which_alternative == 0
      && (GET_CODE (operands[3]) != CONST_INT
	  || INTVAL (operands[3]) > 127
	  || INTVAL (operands[3]) < -128
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
    return \"#\";
  return \"%x5.%s0 [%4=%2%S3],%0\";
}")

;; SImode

(define_insn "*op_swap_sidesi"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(match_operator:SI
	 5 "cris_commutative_orth_op"
	 [(mem:SI
	   (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
		    (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
	  (match_operand:SI 1 "register_operand" "0,0,0")]))
   (set (match_operand:SI 4 "register_operand" "=*2,r,r")
	(plus:SI (match_dup 2)
		 (match_dup 3)))]
  "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
  "*
{
  if (which_alternative == 0
      && (GET_CODE (operands[3]) != CONST_INT
	  || INTVAL (operands[3]) > 127
	  || INTVAL (operands[3]) < -128
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
    return \"#\";
  return \"%x5.%s0 [%4=%2%S3],%0\";
}")

;; Add operations, standard names.

;; Note that for the 'P' constraint, the high part can be -1 or 0.  We
;; output the insn through the 'A' output modifier as "adds.w" and "addq",
;; respectively.
(define_insn "adddi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
	(plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
		 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
  ""
  "@
   addq %2,%M0\;ax\;addq 0,%H0
   subq %n2,%M0\;ax\;subq 0,%H0
   add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
   add.d %M2,%M0\;ax\;add.d %H2,%H0
   add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")

(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
	(plus:SI
	 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r")
	 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))]

;; The last constraint is due to that after reload, the '%' is not
;; honored, and canonicalization doesn't care about keeping the same
;; register as in destination.  This will happen after insn splitting.
;; gcc <= 2.7.2.  FIXME: Check for gcc-2.9x

 ""
 "*
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return \"add.d %2,%0\";
    case 2:
      return \"addq %2,%0\";
    case 3:
      return \"subq %n2,%0\";
    case 4:
      /* 'Known value', but not in -63..63.
	 Check if addu/subu may be used.  */
      if (INTVAL (operands[2]) > 0)
	{
	  if (INTVAL (operands[2]) < 256)
	    return \"addu.b %2,%0\";
	  if (INTVAL (operands[2]) < 65536)
	    return \"addu.w %2,%0\";
	}
      else
	{
	  if (INTVAL (operands[2]) >= -255)
	    return \"subu.b %n2,%0\";
	  if (INTVAL (operands[2]) >= -65535)
	    return \"subu.w %n2,%0\";
	}
      return \"add.d %2,%0\";
    case 6:
      return \"add.d %2,%1,%0\";
    case 5:
      return \"add.d %2,%0\";
    case 7:
      return \"add.d %1,%0\";
    default:
      return \"BOGUS addsi %2+%1 to %0\";
    }
}"
 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])

(define_insn "addhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
		 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
  ""
  "@
   add.w %2,%0
   add.w %2,%0
   addq %2,%0
   subq %n2,%0
   add.w %2,%0
   add.w %2,%1,%0"
  [(set_attr "slottable" "yes,yes,yes,yes,no,no")
   (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])

(define_insn "addqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r,r")
	(plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,r")
		 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
  ""
  "@
   add.b %2,%0
   add.b %2,%0
   addq %2,%0
   subq %n2,%0
   subQ -%b2,%0
   add.b %2,%0
   add.b %2,%1,%0"
  [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
   (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])

;; Subtract.
;;
;; Note that because of insn canonicalization these will *seldom* but
;; rarely be used with a known constant as an operand.

;; Note that for the 'P' constraint, the high part can be -1 or 0.  We
;; output the insn through the 'D' output modifier as "subs.w" and "subq",
;; respectively.
(define_insn "subdi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
	(minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
		  (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
  ""
  "@
   subq %2,%M0\;ax\;subq 0,%H0
   addq %n2,%M0\;ax\;addq 0,%H0
   sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
   sub.d %M2,%M0\;ax\;sub.d %H2,%H0
   sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
	(minus:SI
	 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,r")
	 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
  ""

;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
;; But then again, %2 should not be negative.

  "@
   sub.d %2,%0
   sub.d %2,%0
   subq %2,%0
   addq %n2,%0
   sub%e2.%z2 %2,%0
   sub.d %2,%0
   sub.d %2,%0
   sub.d %2,%1,%0"
  [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])

(define_insn "subhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
	(minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,r")
		  (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
  ""
  "@
   sub.w %2,%0
   sub.w %2,%0
   subq %2,%0
   addq %n2,%0
   sub.w %2,%0
   sub.w %2,%1,%0"
  [(set_attr "slottable" "yes,yes,yes,yes,no,no")
   (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])

(define_insn "subqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
	(minus:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,r")
		  (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))]
  ""
  "@
   sub.b %2,%0
   sub.b %2,%0
   subq %2,%0
   addq %2,%0
   sub.b %2,%0
   sub.b %2,%1,%0"
  [(set_attr "slottable" "yes,yes,yes,yes,no,no")
   (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])

;; CRIS has some add/sub-with-sign/zero-extend instructions.
;;  Although these perform sign/zero-extension to SImode, they are
;; equally applicable for the HImode case.
;; FIXME: Check; GCC should handle the widening.
;;  Note that these must be located after the normal add/sub patterns,
;; so not to get constants into any less specific operands.
;;
;; Extend with add/sub and side-effect.
;;
;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
;;
;; adds/subs/addu/subu bound [rx=ry+rz.S]
;; FIXME: These could have anonymous mode for operand 0.

;; QImode to HImode
;; FIXME: GCC should widen.

(define_insn "*extopqihi_side_biap"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(match_operator:HI
	 6 "cris_additive_operand_extend_operator"
	 [(match_operand:HI 1 "register_operand" "0,0")
	  (match_operator:HI
	   7 "cris_extend_operator"
	   [(mem:QI (plus:SI
		     (mult:SI (match_operand:SI 2 "register_operand" "r,r")
			      (match_operand:SI 3 "const_int_operand" "n,n"))
		     (match_operand:SI 4 "register_operand" "r,r")))])]))
   (set (match_operand:SI 5 "register_operand" "=*4,r")
	(plus:SI (mult:SI (match_dup 2)
			  (match_dup 3))
		 (match_dup 4)))]
  "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
  "@
   #
   %x6%e7.%m7 [%5=%4+%2%T3],%0")

;; QImode to SImode

(define_insn "*extopqisi_side_biap"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(match_operator:SI
	 6 "cris_operand_extend_operator"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operator:SI
	   7 "cris_extend_operator"
	   [(mem:QI (plus:SI
		     (mult:SI (match_operand:SI 2 "register_operand" "r,r")
			      (match_operand:SI 3 "const_int_operand" "n,n"))
		     (match_operand:SI 4 "register_operand" "r,r")))])]))
   (set (match_operand:SI 5 "register_operand" "=*4,r")
	(plus:SI (mult:SI (match_dup 2)
			  (match_dup 3))
		 (match_dup 4)))]
  "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
   && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
  "@
   #
   %x6%e7.%m7 [%5=%4+%2%T3],%0")

;; HImode to SImode

(define_insn "*extophisi_side_biap"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(match_operator:SI
	 6 "cris_operand_extend_operator"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operator:SI
	   7 "cris_extend_operator"
	   [(mem:HI (plus:SI
		     (mult:SI (match_operand:SI 2 "register_operand" "r,r")
			      (match_operand:SI 3 "const_int_operand" "n,n"))
		     (match_operand:SI 4 "register_operand" "r,r")))])]))
   (set (match_operand:SI 5 "register_operand" "=*4,r")
	(plus:SI (mult:SI (match_dup 2)
			  (match_dup 3))
		 (match_dup 4)))]
  "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
   && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
  "@
   #
   %x6%e7.%m7 [%5=%4+%2%T3],%0")


;; [rx=ry+i]
;; FIXME: These could have anonymous mode for operand 0.

;; QImode to HImode

(define_insn "*extopqihi_side"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
	(match_operator:HI
	 5 "cris_additive_operand_extend_operator"
	 [(match_operand:HI 1 "register_operand" "0,0,0")
	  (match_operator:HI
	   6 "cris_extend_operator"
	   [(mem:QI
	     (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
		      (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
		      ))])]))
   (set (match_operand:SI 4 "register_operand" "=*2,r,r")
	(plus:SI (match_dup 2)
		 (match_dup 3)))]
  "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
  "*
{
  if (which_alternative == 0
      && (GET_CODE (operands[3]) != CONST_INT
	  || INTVAL (operands[3]) > 127
	  || INTVAL (operands[3]) < -128
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
    return \"#\";
  return \"%x5%e6.%m6 [%4=%2%S3],%0\";
}")

;; QImode to SImode

(define_insn "*extopqisi_side"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(match_operator:SI
	 5 "cris_operand_extend_operator"
	 [(match_operand:SI 1 "register_operand" "0,0,0")
	  (match_operator:SI
	   6 "cris_extend_operator"
	   [(mem:QI
	     (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
		      (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
		      ))])]))
   (set (match_operand:SI 4 "register_operand" "=*2,r,r")
	(plus:SI (match_dup 2)
		 (match_dup 3)))]

  "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
   && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
  "*
{
  if (which_alternative == 0
      && (GET_CODE (operands[3]) != CONST_INT
	  || INTVAL (operands[3]) > 127
	  || INTVAL (operands[3]) < -128
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
	  || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
    return \"#\";
  return \"%x5%e6.%m6 [%4=%2%S3],%0\";
}")

;; HImode to SImode

(define_insn "*extophisi_side"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(match_operator:SI
	 5 "cris_operand_extend_operator"
	 [(match_operand:SI 1 "register_operand" "0,0,0")
	  (match_operator