📄 cris.md
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case 9: return \"clear.w %0\"; case 4: return \"moveq %1,%0\"; case 6: case 8: if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128) { if (INTVAL (operands[1]) > 0) return \"movu.b %1,%0\"; return \"movs.b %1,%0\"; } return \"move.w %1,%0\"; case 7: return \"movEq %b1,%0\"; default: return \"BOGUS: %1 to %0\"; }}" [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no") (set (attr "cc") (if_then_else (eq_attr "alternative" "7") (const_string "clobber") (const_string "normal")))])(define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+r,r,r,Q>,Q>,g,r,g")) (match_operand:HI 1 "general_operand" "r,Q>,M,M,r,M,g,r"))] "" "@ move.w %1,%0 move.w %1,%0 clear.w %0 clear.w %0 move.w %1,%0 clear.w %0 move.w %1,%0 move.w %1,%0" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])(define_insn "movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,r,g,g,r,r") (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,I,M,r,O,g"))] "" "@ move.b %1,%0 move.b %1,%0 move.b %1,%0 clear.b %0 clear.b %0 moveq %1,%0 clear.b %0 move.b %1,%0 moveq %b1,%0 move.b %1,%0" [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no") (set (attr "cc") (if_then_else (eq_attr "alternative" "8") (const_string "clobber") (const_string "normal")))])(define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r,r,Q>,g,g,r")) (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,M,r,g"))] "" "@ move.b %1,%0 move.b %1,%0 move.b %1,%0 clear.b %0 clear.b %0 clear.b %0 move.b %1,%0 move.b %1,%0" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]);; The valid "quick" bit-patterns are, except for 0.0, denormalized;; values REALLY close to 0, and some NaN:s (I think; their exponent is;; all ones); the worthwhile one is "0.0".;; It will use clear, so we know ALL types of immediate 0 never change cc.(define_insn "movsf" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,g,g,r") (match_operand:SF 1 "general_operand" "r,r,Q>,G,G,G,r,g"))] "" "@ move.d %1,%0 move.d %1,%0 move.d %1,%0 clear.d %0 clear.d %0 clear.d %0 move.d %1,%0 move.d %1,%0" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]);; Sign- and zero-extend insns with standard names.;; Those for integer source operand are ordered with the widest source;; type first.;; Sign-extend.(define_insn "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))] "" "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")(define_insn "extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))] "" "movs.w %1,%M0\;smi %H0\;neg.d %H0,%H0")(define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (sign_extend:SI (match_operand:HI 1 "general_operand" "r,Q>,g")))] "" "movs.w %1,%0" [(set_attr "slottable" "yes,yes,no")])(define_insn "extendqidi2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))] "" "movs.b %1,%M0\;smi %H0\;neg.d %H0,%H0")(define_insn "extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (sign_extend:SI (match_operand:QI 1 "general_operand" "r,Q>,g")))] "" "movs.b %1,%0" [(set_attr "slottable" "yes,yes,no")]);; To do a byte->word exension, extend to dword, exept that the top half;; of the register will be clobbered. FIXME: Perhaps this is not needed.(define_insn "extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))] "" "movs.b %1,%0" [(set_attr "slottable" "yes,yes,no")]);; Zero-extend. The DImode ones are synthesized by gcc, so we don't;; specify them here.(define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")))] "" "movu.w %1,%0" [(set_attr "slottable" "yes,yes,no")])(define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))] "" "movu.b %1,%0" [(set_attr "slottable" "yes,yes,no")]);; Same comment as sign-extend QImode to HImode above applies.(define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))] "" "movu.b %1,%0" [(set_attr "slottable" "yes,yes,no")]);; All kinds of arithmetic and logical instructions.;;;; First, anonymous patterns to match addressing modes with;; side-effects.;;;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).;;;; [rx=ry+rz.S];; FIXME: These could have anonymous mode for operand 0.;; QImode(define_insn "*op_sideqi_biap" [(set (match_operand:QI 0 "register_operand" "=r,r") (match_operator:QI 6 "cris_orthogonal_operator" [(match_operand:QI 1 "register_operand" "0,0") (mem:QI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r")))])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) (match_dup 4)))] "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # %x6.%s0 [%5=%4+%2%T3],%0");; HImode(define_insn "*op_sidehi_biap" [(set (match_operand:HI 0 "register_operand" "=r,r") (match_operator:HI 6 "cris_orthogonal_operator" [(match_operand:HI 1 "register_operand" "0,0") (mem:HI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r")))])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) (match_dup 4)))] "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # %x6.%s0 [%5=%4+%2%T3],%0");; SImode(define_insn "*op_sidesi_biap" [(set (match_operand:SI 0 "register_operand" "=r,r") (match_operator:SI 6 "cris_orthogonal_operator" [(match_operand:SI 1 "register_operand" "0,0") (mem:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r")))])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) (match_dup 4)))] "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # %x6.%s0 [%5=%4+%2%T3],%0");; [rx=ry+i] ([%4=%2+%3]);; FIXME: These could have anonymous mode for operand 0.;; QImode(define_insn "*op_sideqi" [(set (match_operand:QI 0 "register_operand" "=r,r,r") (match_operator:QI 5 "cris_orthogonal_operator" [(match_operand:QI 1 "register_operand" "0,0,0") (mem:QI (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) (set (match_operand:SI 4 "register_operand" "=*2,r,r") (plus:SI (match_dup 2) (match_dup 3)))] "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" "*{ if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 127 || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) return \"#\"; return \"%x5.%s0 [%4=%2%S3],%0\";}");; HImode(define_insn "*op_sidehi" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (match_operator:HI 5 "cris_orthogonal_operator" [(match_operand:HI 1 "register_operand" "0,0,0") (mem:HI (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) (set (match_operand:SI 4 "register_operand" "=*2,r,r") (plus:SI (match_dup 2) (match_dup 3)))] "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" "*{ if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 127 || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) return \"#\"; return \"%x5.%s0 [%4=%2%S3],%0\";}");; SImode(define_insn "*op_sidesi" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (match_operator:SI 5 "cris_orthogonal_operator" [(match_operand:SI 1 "register_operand" "0,0,0") (mem:SI (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) (set (match_operand:SI 4 "register_operand" "=*2,r,r") (plus:SI (match_dup 2) (match_dup 3)))] "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" "*{ if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 127 || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) return \"#\"; return \"%x5.%s0 [%4=%2%S3],%0\";}");; To match all cases for commutative operations we may have to have the;; following pattern for add, or & and. I do not know really, but it does;; not break anything.;;;; FIXME: This really ought to be checked.;;;; op.S [rx=ry+I],rz;;;;; [rx=ry+rz.S];; FIXME: These could have anonymous mode for operand 0.;; QImode(define_insn "*op_swap_sideqi_biap" [(set (match_operand:QI 0 "register_operand" "=r,r") (match_operator:QI 6 "cris_commutative_orth_op" [(mem:QI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r"))) (match_operand:QI 1 "register_operand" "0,0")])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) (match_dup 4)))] "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # %x6.%s0 [%5=%4+%2%T3],%0");; HImode(define_insn "*op_swap_sidehi_biap" [(set (match_operand:HI 0 "register_operand" "=r,r") (match_operator:HI 6 "cris_commutative_orth_op" [(mem:HI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r"))) (match_operand:HI 1 "register_operand" "0,0")])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) (match_dup 4)))] "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # %x6.%s0 [%5=%4+%2%T3],%0");; SImode(define_insn "*op_swap_sidesi_biap" [(set (match_operand:SI 0 "register_operand" "=r,r") (match_operator:SI 6 "cris_commutative_orth_op" [(mem:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r"))) (match_operand:SI 1 "register_operand" "0,0")])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) (match_dup 4)))] "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # %x6.%s0 [%5=%4+%2%T3],%0");; [rx=ry+i] ([%4=%2+%3]);; FIXME: These could have anonymous mode for operand 0.;; QImode(define_insn "*op_swap_sideqi"
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