i960.md

linux下的gcc编译器

		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{ operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }")

;; Now the normal branch insns (forward and reverse).

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "comparison_operator"
				      [(reg:CC 36) (const_int 0)])
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "b%C0%+ %l1"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "comparison_operator"
				      [(reg:CC 36) (const_int 0)])
		      (pc)
		      (label_ref (match_operand 1 "" ""))))]
  ""
  "b%I0%+ %l1"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "comparison_operator"
				      [(reg:CC_UNS 36) (const_int 0)])
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "b%C0%+ %l1"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "comparison_operator"
				      [(reg:CC_UNS 36) (const_int 0)])
		      (pc)
		      (label_ref (match_operand 1 "" ""))))]
  ""
  "b%I0%+ %l1"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "comparison_operator"
			 [(match_operand:SI 1 "arith_operand" "d")
			  (match_operand:SI 2 "arith_operand" "dI")])
	 (label_ref (match_operand 3 "" ""))
	 (pc)))]
  ""
  "cmp%S0%B0%R0%+	%2,%1,%l3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (match_operator 0 "comparison_operator"
			 [(match_operand:SI 1 "arith_operand" "d")
			  (match_operand:SI 2 "arith_operand" "dI")])
	 (pc)
	 (label_ref (match_operand 3 "" ""))))]
  ""
  "cmp%S0%B0%X0%+	%2,%1,%l3"
  [(set_attr "type" "branch")])

;; Now the trap instructions.  The i960 appears to only have conditional
;; traps...

(define_insn ("trap")
  [(trap_if (const_int 1) (const_int 0))]
  ""
  "cmpo g0,g0 ; faulte.t")

(define_expand "conditional_trap"
  [(trap_if (match_operator 0 "comparison_operator"
	     [(match_dup 2) (const_int 0)]) 
	    (match_operand 1 "const_int_operand" "i"))]
  ""
  "
{
  operands[2] = gen_compare_reg (GET_CODE (operands[0]), 
				 i960_compare_op0, i960_compare_op1);
}")

(define_insn ""
  [(trap_if (match_operator 0 "comparison_operator"
	     [(reg:CC 36) (const_int 0)]) 
	    (match_operand 1 "const_int_operand" "i"))]
  ""
  "fault%C0.f")

(define_insn ""
  [(trap_if (match_operator 0 "comparison_operator"
	     [(reg:CC_UNS 36) (const_int 0)]) 
	    (match_operand 1 "const_int_operand" "i"))]
  ""
  "fault%C0.f")

;; Normal move instructions.
;; This code is based on the sparc machine description.

(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, SImode))
    DONE;
}")

;; The store case can not be separate, because reload may convert a register
;; to register move insn to a store (or load) insn without rerecognizing
;; the insn.

;; The i960 does not have any store constant to memory instruction.  However,
;; the calling convention is defined so that the arg pointer when it is not
;; overwise being used is zero.  Thus, we can handle store zero to memory
;; by storing an unused arg pointer.  The arg pointer will be unused if
;; current_function_args_size is zero and this is not a stdarg
;; function.  This value of the former variable is not valid until after
;; all rtl generation is complete, including function inlining (because a
;; function that doesn't need an arg pointer may be inlined into a function
;; that does need an arg pointer), so we must also check that
;; rtx_equal_function_value_matters is zero.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
	(match_operand:SI 1 "general_operand" "dI,i,m,dJ"))]
  "(current_function_args_size == 0
    && current_function_stdarg == 0
    && rtx_equal_function_value_matters == 0)
   && (register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode)
       || operands[1] == const0_rtx)"
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
	{
	  if (GET_CODE (operands[1]) == REG)
	    return \"lda	(%1),%0\";
	  else
	    return \"lda	%1,%0\";
	}
      return \"mov	%1,%0\";
    case 1:
      return i960_output_ldconst (operands[0], operands[1]);
    case 2:
      return \"ld	%1,%0\";
    case 3:
      if (operands[1] == const0_rtx)
	return \"st	g14,%0\";
      return \"st	%1,%0\";      
    default:
      abort();
    }
}"
  [(set_attr "type" "move,address,load,store")
   (set_attr "length" "*,3,*,*")])

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
	(match_operand:SI 1 "general_operand" "dI,i,m,d"))]
  "(current_function_args_size != 0
    || current_function_stdarg != 0
    || rtx_equal_function_value_matters != 0)
   && (register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode))"
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
	{
	  if (GET_CODE (operands[1]) == REG)
	    return \"lda	(%1),%0\";
	  else
	    return \"lda	%1,%0\";
	}
      return \"mov	%1,%0\";
    case 1:
      return i960_output_ldconst (operands[0], operands[1]);
    case 2:
      return \"ld	%1,%0\";
    case 3:
      return \"st	%1,%0\";      
    default:
      abort();
    }
}"
  [(set_attr "type" "move,address,load,store")
   (set_attr "length" "*,3,*,*")])

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "")
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, HImode))
    DONE;
}")

;; Special pattern for zero stores to memory for functions which don't use
;; the arg pointer.

;; The store case can not be separate.  See above.
(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
	(match_operand:HI 1 "general_operand" "dI,i,m,dJ"))]
  "(current_function_args_size == 0
    && current_function_stdarg == 0
    && rtx_equal_function_value_matters == 0)
   && (register_operand (operands[0], HImode)
       || register_operand (operands[1], HImode)
       || operands[1] == const0_rtx)"
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
	{
	  if (GET_CODE (operands[1]) == REG)
	    return \"lda	(%1),%0\";
	  else
	    return \"lda	%1,%0\";
	}
      return \"mov	%1,%0\";
    case 1:
      return i960_output_ldconst (operands[0], operands[1]);
    case 2:
      return \"ldos	%1,%0\";
    case 3:
      if (operands[1] == const0_rtx)
	return \"stos	g14,%0\";
      return \"stos	%1,%0\";
    default:
      abort();
    }
}"
  [(set_attr "type" "move,misc,load,store")
   (set_attr "length" "*,3,*,*")])

;; The store case can not be separate.  See above.
(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
	(match_operand:HI 1 "general_operand" "dI,i,m,d"))]
  "(current_function_args_size != 0
    || current_function_stdarg != 0
    || rtx_equal_function_value_matters != 0)
   && (register_operand (operands[0], HImode)
       || register_operand (operands[1], HImode))"
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
	{
	  if (GET_CODE (operands[1]) == REG)
	    return \"lda	(%1),%0\";
	  else
	    return \"lda	%1,%0\";
	}
      return \"mov	%1,%0\";
    case 1:
      return i960_output_ldconst (operands[0], operands[1]);
    case 2:
      return \"ldos	%1,%0\";
    case 3:
      return \"stos	%1,%0\";
    default:
      abort();
    }
}"
  [(set_attr "type" "move,misc,load,store")
   (set_attr "length" "*,3,*,*")])

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, QImode))
    DONE;
}")

;; The store case can not be separate.  See comment above.
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
	(match_operand:QI 1 "general_operand" "dI,i,m,dJ"))]
  "(current_function_args_size == 0
    && current_function_stdarg == 0
    && rtx_equal_function_value_matters == 0)
   && (register_operand (operands[0], QImode)
       || register_operand (operands[1], QImode)
       || operands[1] == const0_rtx)"
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
	{
	  if (GET_CODE (operands[1]) == REG)
	    return \"lda	(%1),%0\";
	  else
	    return \"lda	%1,%0\";
	}
      return \"mov	%1,%0\";
    case 1:
      return i960_output_ldconst (operands[0], operands[1]);
    case 2:
      return \"ldob	%1,%0\";
    case 3:
      if (operands[1] == const0_rtx)
	return \"stob	g14,%0\";
      return \"stob	%1,%0\";
    default:
      abort();
    }
}"
  [(set_attr "type" "move,misc,load,store")
   (set_attr "length" "*,3,*,*")])

;; The store case can not be separate.  See comment above.
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
	(match_operand:QI 1 "general_operand" "dI,i,m,d"))]
  "(current_function_args_size != 0
    || current_function_stdarg != 0
    || rtx_equal_function_value_matters != 0)
   && (register_operand (operands[0], QImode)
       || register_operand (operands[1], QImode))"
  "*
{
  switch (which_alternative)
    {
    case 0:
      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
	{
	  if (GET_CODE (operands[1]) == REG)
	    return \"lda	(%1),%0\";
	  else
	    return \"lda	%1,%0\";
	}
      return \"mov	%1,%0\";
    case 1:
      return i960_output_ldconst (operands[0], operands[1]);
    case 2:
      return \"ldob	%1,%0\";
    case 3:
      return \"stob	%1,%0\";
    default:
      abort();
    }
}"
  [(set_attr "type" "move,misc,load,store")
   (set_attr "length" "*,3,*,*")])

(define_expand "movdi"
  [(set (match_operand:DI 0 "general_operand" "")
	(match_operand:DI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, DImode))
    DONE;
}")

;; The store case can not be separate.  See comment above.
(define_insn ""
  [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m,o")
	(match_operand:DI 1 "general_operand" "d,I,i,m,d,J"))]
  "(current_function_args_size == 0
    && current_function_stdarg == 0
    && rtx_equal_function_value_matters == 0)
   && (register_operand (operands[0], DImode)
       || register_operand (operands[1], DImode)
       || operands[1] == const0_rtx)"
  "*
{
  switch (which_alternative)
    {
    case 0:
    case 1:
    case 3:
    case 4:
      return i960_output_move_double (operands[0], operands[1]);
    case 2:
      return i960_output_ldconst (operands[0], operands[1]);
    case 5:
       return i960_output_move_double_zero (operands[0]);
    default:
      abort();
    }
}"
  [(set_attr "type" "move,move,load,load,store,store")])

;; The store case can not be separate.  See comment above.
(define_insn ""
  [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m")
	(match_operand:DI 1 "general_operand" "d,I,i,m,d"))]
  "(current_function_args_size != 0
    || current_function_stdarg != 0
    || rtx_equal_function_value_matters != 0)
   && (register_operand (operands[0], DImode)
       || register_operand (operands[1], DImode))"
  "*
{
  switch (which_alternative)
    {
    case 0:
    case 1:
    case 3:
    case 4:
      return i960_output_move_double (operands[0], operands[1]);
    case 2:
      return i960_output_ldconst (operands[0], operands[1]);
    default:
      abort();
    }
}"
  [(set_attr "type" "move,move,load,load,store")])

(define_insn "*store_unaligned_di_reg"
  [(set (match_operand:DI 0 "general_operand" "=d,m")
	(match_operand:DI 1 "register_operand" "d,d"))
   (clobber (match_scratch:SI 2 "=X,&d"))]
  ""
  "*
{
  if (which_alternative == 0)
    return i960_output_move_double (operands[0], operands[1]);
    
  operands[3] = gen_rtx_MEM (word_mode, operands[2]);
  operands[4] = adjust_address (operands[3], word_mode, UNITS_PER_WORD);
  return \"lda	%0,%2\;st	%1,%3\;st	%D1,%4\";
}"
  [(set_attr "type" "move,store")])

(define_expand "movti"
  [(set (match_operand:TI 0 "general_operand" "")
	(match_operand:TI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, TImode))
    DONE;
}")

;; The store case can not be separate.  See comment above.
(define_insn ""
  [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m,o")
	(match_operand:TI 1 "general_operand" "d,I,i,m,d,J"))]
  "(current_function_args_size == 0
    && current_function_stdarg == 0