i960.h

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/* Definitions of target machine for GNU compiler, for Intel 80960
   Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2002
   Free Software Foundation, Inc.
   Contributed by Steven McGeady, Intel Corp.
   Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
   Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

/* Note that some other tm.h files may include this one and then override
   many of the definitions that relate to assembler syntax.  */

#define MULTILIB_DEFAULTS { "mnumerics" }

/* Names to predefine in the preprocessor for this target machine.  */
#define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu=i960 -Amachine=i960"

/* Name to predefine in the preprocessor for processor variations.
   -mic* options make characters signed by default.  */
#define	CPP_SPEC "%{mic*:-D__i960 -fsigned-char\
			%{mka:-D__i960KA}%{mkb:-D__i960KB}\
			%{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\
			%{mrp:-D__i960RP}\
			%{msa:-D__i960SA}%{msb:-D__i960SB}\
			%{mmc:-D__i960MC}\
			%{mca:-D__i960CA}%{mcc:-D__i960CC}\
			%{mcf:-D__i960CF}}\
	%{msoft-float:-D_SOFT_FLOAT}\
	%{mka:-D__i960KA__ -D__i960_KA__}\
	%{mkb:-D__i960KB__ -D__i960_KB__}\
	%{msa:-D__i960SA__ -D__i960_SA__}\
	%{msb:-D__i960SB__ -D__i960_SB__}\
	%{mmc:-D__i960MC__ -D__i960_MC__}\
	%{mca:-D__i960CA__ -D__i960_CA__}\
	%{mcc:-D__i960CC__ -D__i960_CC__}\
	%{mcf:-D__i960CF__ -D__i960_CF__}\
	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
		%{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}\
	%{mlong-double-64:-D__LONG_DOUBLE_64__}"

/* Specs for the compiler, to handle processor variations. 
   If the user gives an explicit -gstabs or -gcoff option, then do not
   try to add an implicit one, as this will fail. 
   -mic* options make characters signed by default.  */
#define CC1_SPEC \
	"%{mic*:-fsigned-char}\
%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
	 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
		       %{mcoff:%{g*:-gcoff}}\
		       %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"

/* Specs for the assembler, to handle processor variations.
   For compatibility with Intel's gnu960 tool chain, pass -A options to
   the assembler.  */
#define ASM_SPEC \
	"%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
	%{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
        %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-AKB}}}}}}}}}}}}\
	%{mlink-relax:-linkrelax}"

/* Specs for the linker, to handle processor variations.
   For compatibility with Intel's gnu960 tool chain, pass -F and -A options
   to the linker.  */
#define LINK_SPEC \
	"%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
	%{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
        %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
	%{mbout:-Fbout}%{mcoff:-Fcoff}\
	%{mlink-relax:-relax}"

/* Specs for the libraries to link with, to handle processor variations.
   Compatible with Intel's gnu960 tool chain.  */
#define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
	  %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"

/* Defining the macro shows we can debug even without a frame pointer.
   Actually, we can debug without FP.  But defining the macro results in
   that -O means FP elimination.  Addressing through sp requires
   negative offset and more one word addressing in the most cases
   (offsets except for 0-4095 require one more word).  Therefore we've
   not defined the macro.  */
/*#define CAN_DEBUG_WITHOUT_FP*/

/* Do leaf procedure and tail call optimizations for -O2 and higher.  */
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)	\
{						\
  if ((LEVEL) >= 2)				\
    {						\
      target_flags |= TARGET_FLAG_LEAFPROC;	\
      target_flags |= TARGET_FLAG_TAILCALL;	\
    }						\
}

/* Print subsidiary information on the compiler version in use.  */
#define TARGET_VERSION fprintf (stderr," (intel 80960)");

/* Generate DBX debugging information.  */
#define DBX_DEBUGGING_INFO 1

/* Generate SDB style debugging information.  */
#define SDB_DEBUGGING_INFO 1
#define EXTENDED_SDB_BASIC_TYPES

/* Generate DBX_DEBUGGING_INFO by default.  */
#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG

/* Redefine this to print in hex.  No value adjustment is necessary
   anymore.  */
#define PUT_SDB_TYPE(A) \
  fprintf (asm_out_file, "\t.type\t0x%x;", A)

/* Handle pragmas for compatibility with Intel's compilers.  */

extern int i960_maxbitalignment;
extern int i960_last_maxbitalignment;

#define REGISTER_TARGET_PRAGMAS(PFILE) do {			\
  cpp_register_pragma (PFILE, 0, "align", i960_pr_align);	\
  cpp_register_pragma (PFILE, 0, "noalign", i960_pr_noalign);	\
} while (0)

/* Run-time compilation parameters selecting different hardware subsets.  */

/* 960 architecture with floating-point.  */
#define TARGET_FLAG_NUMERICS	0x01
#define TARGET_NUMERICS		(target_flags & TARGET_FLAG_NUMERICS)

/* 960 architecture with memory management.  */
/* ??? Not used currently.  */
#define	TARGET_FLAG_PROTECTED	0x02
#define	TARGET_PROTECTED	(target_flags & TARGET_FLAG_PROTECTED)

/* The following three are mainly used to provide a little sanity checking
   against the -mARCH flags given. The Jx series, for the purposes of
   gcc, is a Kx with a data cache.  */

/* Nonzero if we should generate code for the KA and similar processors.
   No FPU, no microcode instructions.  */
#define TARGET_FLAG_K_SERIES	0x04
#define TARGET_K_SERIES		(target_flags & TARGET_FLAG_K_SERIES)

/* Nonzero if we should generate code for the MC processor.
   Not really different from KB for our purposes.  */
#define	TARGET_FLAG_MC		0x08
#define TARGET_MC 		(target_flags & TARGET_FLAG_MC)

/* Nonzero if we should generate code for the CA processor.
   Enables different optimization strategies.  */
#define	TARGET_FLAG_C_SERIES	0x10
#define	TARGET_C_SERIES 	(target_flags & TARGET_FLAG_C_SERIES)

/* Nonzero if we should generate leaf-procedures when we find them.
   You may not want to do this because leaf-proc entries are
   slower when not entered via BAL - this would be true when
   a linker not supporting the optimization is used.  */
#define	TARGET_FLAG_LEAFPROC	0x20
#define	TARGET_LEAFPROC		(target_flags & TARGET_FLAG_LEAFPROC)

/* Nonzero if we should perform tail-call optimizations when we find them.
   You may not want to do this because the detection of cases where
   this is not valid is not totally complete.  */
#define	TARGET_FLAG_TAILCALL	0x40
#define	TARGET_TAILCALL		(target_flags & TARGET_FLAG_TAILCALL)

/* Nonzero if use of a complex addressing mode is a win on this implementation.
   Complex addressing modes are probably not worthwhile on the K-series,
   but they definitely are on the C-series.  */
#define	TARGET_FLAG_COMPLEX_ADDR 0x80
#define	TARGET_COMPLEX_ADDR	(target_flags & TARGET_FLAG_COMPLEX_ADDR)

/* Align code to 8 byte boundaries for faster fetching.  */
#define	TARGET_FLAG_CODE_ALIGN	0x100
#define	TARGET_CODE_ALIGN	(target_flags  & TARGET_FLAG_CODE_ALIGN)

/* Append branch prediction suffixes to branch opcodes.  */
/* ??? Not used currently.  */
#define	TARGET_FLAG_BRANCH_PREDICT 0x200
#define	TARGET_BRANCH_PREDICT	(target_flags  & TARGET_FLAG_BRANCH_PREDICT)

/* Forces prototype and return promotions.  */
/* ??? This does not work.  */
#define	TARGET_FLAG_CLEAN_LINKAGE 0x400
#define	TARGET_CLEAN_LINKAGE	(target_flags & TARGET_FLAG_CLEAN_LINKAGE)

/* For compatibility with iC960 v3.0.  */
#define	TARGET_FLAG_IC_COMPAT3_0 0x800 
#define	TARGET_IC_COMPAT3_0	(target_flags & TARGET_FLAG_IC_COMPAT3_0)

/* For compatibility with iC960 v2.0.  */
#define	TARGET_FLAG_IC_COMPAT2_0 0x1000
#define	TARGET_IC_COMPAT2_0	(target_flags & TARGET_FLAG_IC_COMPAT2_0)

/* If no unaligned accesses are to be permitted.  */
#define	TARGET_FLAG_STRICT_ALIGN 0x2000
#define	TARGET_STRICT_ALIGN	(target_flags & TARGET_FLAG_STRICT_ALIGN)

/* For compatibility with iC960 assembler.  */
#define	TARGET_FLAG_ASM_COMPAT	0x4000
#define	TARGET_ASM_COMPAT	(target_flags & TARGET_FLAG_ASM_COMPAT)

/* For compatibility with the gcc960 v1.2 compiler.  Use the old structure
   alignment rules.  Also, turns on STRICT_ALIGNMENT.  */
#define TARGET_FLAG_OLD_ALIGN	0x8000
#define TARGET_OLD_ALIGN	(target_flags & TARGET_FLAG_OLD_ALIGN)

/* Nonzero if long doubles are to be 64 bits.  Useful for soft-float targets
   if 80 bit long double support is missing.  */
#define TARGET_FLAG_LONG_DOUBLE_64	0x10000
#define TARGET_LONG_DOUBLE_64	(target_flags & TARGET_FLAG_LONG_DOUBLE_64)

extern int target_flags;

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

/* ??? Not all ten of these architecture variations actually exist, but I
   am not sure which are real and which aren't.  */

#define TARGET_SWITCHES  \
  { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR),		\
       N_("Generate SA code")},						\
    {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES|			\
			TARGET_FLAG_COMPLEX_ADDR),			\
       N_("Generate SB code")},						\
/*  {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|			\
			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR),	\
       N_("Generate SC code")}, */					\
    {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR),		\
       N_("Generate KA code")},						\
    {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES|			\
			TARGET_FLAG_COMPLEX_ADDR),			\
       N_("Generate KB code")},						\
/*  {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|			\
			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR),	\
       N_("Generate KC code")}, */					\
    {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR),		\
       N_("Generate JA code")},						\
    {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR),		\
       N_("Generate JD code")},						\
    {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES|			\
			TARGET_FLAG_COMPLEX_ADDR),			\
       N_("Generate JF code")},						\
    {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR),		\
       N_("generate RP code")},						\
    {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|			\
			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR),	\
       N_("Generate MC code")},						\
    {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|		\
			TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
       N_("Generate CA code")},						\
/*  {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|			\
			TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\
       N_("Generate CB code")},						\
    {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|			\
			TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
			TARGET_FLAG_CODE_ALIGN),			\
       N_("Generate CC code")}, */					\
    {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|		\
			TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
       N_("Generate CF code")},						\
    {"numerics", (TARGET_FLAG_NUMERICS),				\
       N_("Use hardware floating point instructions")},			\
    {"soft-float", -(TARGET_FLAG_NUMERICS),				\
       N_("Use software floating point")},				\
    {"leaf-procedures", TARGET_FLAG_LEAFPROC,				\
       N_("Use alternate leaf function entries")},			\
    {"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC),			\
       N_("Do not use alternate leaf function entries")},		\
    {"tail-call", TARGET_FLAG_TAILCALL,					\
       N_("Perform tail call optimization")},				\
    {"no-tail-call", -(TARGET_FLAG_TAILCALL),				\
       N_("Do not perform tail call optimization")},			\
    {"complex-addr", TARGET_FLAG_COMPLEX_ADDR, 				\
       N_("Use complex addressing modes")},				\
    {"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR),			\
       N_("Do not use complex addressing modes")},			\
    {"code-align", TARGET_FLAG_CODE_ALIGN,				\
       N_("Align code to 8 byte boundary")},				\
    {"no-code-align", -(TARGET_FLAG_CODE_ALIGN),			\
       N_("Do not align code to 8 byte boundary")},			\
/*  {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE),			\
       N_("Force use of prototypes")},					\
    {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE),			\
       N_("Do not force use of prototypes")}, */			\
    {"ic-compat", TARGET_FLAG_IC_COMPAT2_0,				\
       N_("Enable compatibility with iC960 v2.0")},			\
    {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0,				\
       N_("Enable compatibility with iC960 v2.0")},			\
    {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0,				\
       N_("Enable compatibility with iC960 v3.0")},			\
    {"asm-compat", TARGET_FLAG_ASM_COMPAT,				\
       N_("Enable compatibility with ic960 assembler")},		\
    {"intel-asm", TARGET_FLAG_ASM_COMPAT,				\
       N_("Enable compatibility with ic960 assembler")},		\
    {"strict-align", TARGET_FLAG_STRICT_ALIGN,				\
       N_("Do not permit unaligned accesses")},				\
    {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN),			\
       N_("Permit unaligned accesses")},				\
    {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN),	\
       N_("Layout types like Intel's v1.3 gcc")},			\
    {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN),	\
       N_("Do not layout types like Intel's v1.3 gcc")},		\
    {"long-double-64", TARGET_FLAG_LONG_DOUBLE_64,			\
       N_("Use 64 bit long doubles")},					\
    {"link-relax", 0,							\
       N_("Enable linker relaxation")},					\
    {"no-link-relax", 0,						\
       N_("Do not enable linker relaxation")},				\
    SUBTARGET_SWITCHES                                                  \
    { "", TARGET_DEFAULT,						\
	NULL}}

/* This are meant to be redefined in the host dependent files */
#define SUBTARGET_SWITCHES

/* Override conflicting target switch options.
   Doesn't actually detect if more than one -mARCH option is given, but
   does handle the case of two blatantly conflicting -mARCH options.  */
#define OVERRIDE_OPTIONS  i960_initialize ()

/* Don't enable anything by default.  The user is expected to supply a -mARCH
   option.  If none is given, then -mka is added by CC1_SPEC.  */
#define TARGET_DEFAULT 0

/* Target machine storage layout.  */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.
   The i960 case be either big endian or little endian.  We only support
   little endian, which is the most common.  */
#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword number is lowest
   numbered.  */
#define WORDS_BIG_ENDIAN 0

/* Bitfields cannot cross word boundaries.  */
#define BITFIELD_NBYTES_LIMITED 1

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 4

/* Width in bits of a long double.  */
#define	LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 128)
#define MAX_LONG_DOUBLE_TYPE_SIZE 128