c4x.md

linux下的gcc编译器

   (set (reg:CC 21)
        (compare:CC (match_dup 0) (const_int 0)))]
  ""
  "ldi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])

(define_insn "*movqi_set"
  [(set (reg:CC 21)
        (compare:CC (match_operand:QI 1 "src_operand" "rIm") 
                    (const_int 0)))
   (set (match_operand:QI 0 "ext_reg_operand" "=d")
        (match_dup 1))]
  ""
  "ldi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])

; This pattern probably gets in the way and requires a scratch register
; when a simple compare with zero will suffice.
;(define_insn "*movqi_test"
; [(set (reg:CC 21)
;       (compare:CC (match_operand:QI 1 "src_operand" "rIm") 
;                   (const_int 0)))
;  (clobber (match_scratch:QI 0 "=d"))]
; ""
; "@
;  ldi\\t%1,%0"
;  [(set_attr "type" "unarycc")
;   (set_attr "data" "int16")])

;  If one of the operands is not a register, then we should
;  emit two insns, using a scratch register.  This will produce
;  better code in loops if the source operand is invariant, since
;  the source reload can be optimized out.  During reload we cannot
;  use change_address or force_reg which will allocate new pseudo regs.

;  Unlike most other insns, the move insns can't be split with
;  different predicates, because register spilling and other parts of
;  the compiler, have memoized the insn number already.

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
        (match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (c4x_emit_move_sequence (operands, QImode))
    DONE;
}")


; As far as GCC is concerned, the moves are performed in parallel
; thus it must be convinced that there is no aliasing.
; It also assumes that the input operands are simultaneously loaded
; and then the output operands are simultaneously stored.
; With the C4x, if there are parallel stores to the same address
; both stores are executed.
; If there is a parallel load and store to the same address,
; the load is performed first.
; The problem with this pattern is that reload can spoil
; the show when it eliminates a reference to the frame pointer.
; This can invalidate the memory addressing mode, i.e., when
; the displacement is greater than 1.
(define_insn "movqi_parallel"
  [(set (match_operand:QI 0 "parallel_operand" "=q,S<>!V,q,S<>!V")
        (match_operand:QI 1 "parallel_operand" "S<>!V,q,S<>!V,q"))
   (set (match_operand:QI 2 "parallel_operand" "=q,S<>!V,S<>!V,q")
        (match_operand:QI 3 "parallel_operand" "S<>!V,q,q,S<>!V"))]
  "TARGET_PARALLEL && valid_parallel_load_store (operands, QImode)"
  "@
   ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2
   sti1\\t%1,%0\\n||\\tsti2\\t%3,%2
   ldi\\t%1,%0\\n||\\tsti\\t%3,%2
   ldi\\t%3,%2\\n||\\tsti\\t%1,%0"
  [(set_attr "type" "load_load,store_store,load_store,store_load")])

;
; PUSH/POP
;
(define_insn "pushqi"
  [(set (mem:QI (pre_inc:QI (reg:QI 20)))
        (match_operand:QI 0 "reg_operand" "r"))]
  ""
  "push\\t%0"
  [(set_attr "type" "push")])

(define_insn "push_st"
  [(set (mem:QI (pre_inc:QI (reg:QI 20))) (unspec:QI [(reg:QI 21)] 14))
   (use (reg:QI 21))]
  ""
  "push\\tst"
  [(set_attr "type" "push")])

(define_insn "push_dp"
  [(set (mem:QI (pre_inc:QI (reg:QI 20))) (unspec:QI [(reg:QI 16)] 16))
   (use (reg:QI 16))]
  ""
  "push\\tdp"
  [(set_attr "type" "push")])

(define_insn "popqi"
  [(set (match_operand:QI 0 "reg_operand" "=r")
        (mem:QI (post_dec:QI (reg:QI 20))))
   (clobber (reg:CC 21))]
  ""
  "pop\\t%0"
  [(set_attr "type" "pop")])

(define_insn "pop_st"
  [(set (unspec:QI [(reg:QI 21)] 15) (mem:QI (post_dec:QI (reg:QI 20))))
   (clobber (reg:CC 21))]
  ""
  "pop\\tst"
  [(set_attr "type" "pop")])

(define_insn "pop_dp"
  [(set (unspec:QI [(reg:QI 16)] 17) (mem:QI (post_dec:QI (reg:QI 20))))
   (clobber (reg:CC 16))]
  ""
  "pop\\tdp"
  [(set_attr "type" "pop")])

(define_insn "popqi_unspec"
  [(set (unspec:QI [(match_operand:QI 0 "reg_operand" "=r")] 18)
        (mem:QI (post_dec:QI (reg:QI 20))))
   (clobber (match_dup 0))
   (clobber (reg:CC 21))]
  ""
  "pop\\t%0"
  [(set_attr "type" "pop")])

;
; ABSI
;
(define_expand "absqi2"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (abs:QI (match_operand:QI 1 "src_operand" "")))
              (clobber (reg:CC_NOOV 21))])]
  ""
  "")

(define_insn "*absqi2_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (abs:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
   (clobber (reg:CC_NOOV 21))]
  ""
  "absi\\t%1,%0"
  [(set_attr "type" "unarycc,unary")
   (set_attr "data" "int16,int16")])

(define_insn "*absqi2_noclobber"
  [(set (match_operand:QI 0 "std_reg_operand" "=c")
        (abs:QI (match_operand:QI 1 "src_operand" "rIm")))]
  ""
  "absi\\t%1,%0"
  [(set_attr "type" "unary")
   (set_attr "data" "int16")])

(define_split
  [(set (match_operand:QI 0 "std_reg_operand" "")
        (abs:QI (match_operand:QI 1 "src_operand" "")))
   (clobber (reg:CC_NOOV 21))]
  "reload_completed"
  [(set (match_dup 0)
        (abs:QI (match_dup 1)))]
  "")

(define_insn "*absqi2_test"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (clobber (match_scratch:QI 0 "=d"))]
  ""
  "absi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])

(define_insn "*absqi2_set"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (set (match_operand:QI 0 "ext_reg_operand" "=d")
        (abs:QI (match_dup 1)))]
  ""
  "absi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])        

;
; NEGI
;
(define_expand "negqi2"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (neg:QI (match_operand:QI 1 "src_operand" "")))
              (clobber (reg:CC_NOOV 21))])]
""
"")

(define_insn "*negqi2_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (neg:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
   (clobber (reg:CC_NOOV 21))]
  ""
  "negi\\t%1,%0"
  [(set_attr "type" "unarycc,unary")
   (set_attr "data" "int16,int16")])

(define_insn "*negqi2_noclobber"
  [(set (match_operand:QI 0 "std_reg_operand" "=c")
        (neg:QI (match_operand:QI 1 "src_operand" "rIm")))]
  ""
  "negi\\t%1,%0"
  [(set_attr "type" "unary")
   (set_attr "data" "int16")])

(define_split
  [(set (match_operand:QI 0 "std_reg_operand" "")
        (neg:QI (match_operand:QI 1 "src_operand" "")))
   (clobber (reg:CC_NOOV 21))]
  "reload_completed"
  [(set (match_dup 0)
        (neg:QI (match_dup 1)))]
  "")

(define_insn "*negqi2_test"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (clobber (match_scratch:QI 0 "=d"))]
  ""
  "negi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])

(define_insn "*negqi2_set"
  [(set (reg:CC_NOOV 21)
        (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
                         (const_int 0)))
   (set (match_operand:QI 0 "ext_reg_operand" "=d")
        (neg:QI (match_dup 1)))]
  ""
  "negi\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])        

(define_insn "*negbqi2_clobber"
  [(set (match_operand:QI 0 "ext_reg_operand" "=d")
        (neg:QI (match_operand:QI 1 "src_operand" "rIm")))
   (use (reg:CC_NOOV 21))
   (clobber (reg:CC_NOOV 21))]
  ""
  "negb\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "int16")])        

;
; NOT
;
(define_expand "one_cmplqi2"
  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
                   (not:QI (match_operand:QI 1 "lsrc_operand" "")))
              (clobber (reg:CC 21))])]
  ""
  "")

(define_insn "*one_cmplqi2_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (not:QI (match_operand:QI 1 "lsrc_operand" "rLm,rLm")))
   (clobber (reg:CC 21))]
  ""
  "not\\t%1,%0"
  [(set_attr "type" "unarycc,unary")
   (set_attr "data" "uint16,uint16")])

(define_insn "*one_cmplqi2_noclobber"
  [(set (match_operand:QI 0 "std_reg_operand" "=c")
        (not:QI (match_operand:QI 1 "lsrc_operand" "rLm")))]
  ""
  "not\\t%1,%0"
  [(set_attr "type" "unary")
   (set_attr "data" "uint16")])

(define_split
  [(set (match_operand:QI 0 "std_reg_operand" "")
        (not:QI (match_operand:QI 1 "lsrc_operand" "")))
   (clobber (reg:CC 21))]
  "reload_completed"
  [(set (match_dup 0)
        (not:QI (match_dup 1)))]
  "")

(define_insn "*one_cmplqi2_test"
  [(set (reg:CC 21)
        (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
                    (const_int 0)))
   (clobber (match_scratch:QI 0 "=d"))]
  ""
  "not\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "uint16")])

(define_insn "*one_cmplqi2_set"
  [(set (reg:CC 21)
        (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
                    (const_int 0)))
   (set (match_operand:QI 0 "ext_reg_operand" "=d")        
        (not:QI (match_dup 1)))]
  ""
  "not\\t%1,%0"
  [(set_attr "type" "unarycc")
   (set_attr "data" "uint16")])        

(define_insn "*one_cmplqi2_const_clobber"
  [(set (match_operand:QI 0 "reg_operand" "=d,c")
        (match_operand:QI 1 "not_const_operand" "N,N"))
   (clobber (reg:CC 21))]
  ""
  "@
   not\\t%N1,%0
   not\\t%N1,%0"
   [(set_attr "type" "unarycc,unary")
    (set_attr "data" "not_uint16,not_uint16")])

; movqi can use this for loading an integer that can't normally
; fit into a 16-bit signed integer.  The drawback is that it cannot
; go into R0-R11 since that will clobber the CC and movqi shouldn't
; do that.  This can cause additional rel