c4x.md

linux下的gcc编译器

   && reload_completed
   && std_reg_operand (operands[0], QImode)"
  [(set (match_dup 0) (match_dup 2))
   (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
  "
{
   operands[2] = GEN_INT (INTVAL (operands[1]) & ~0xffff);
   operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))
   (clobber (reg:QI 16))]
  "TARGET_C3X && ! TARGET_SMALL
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && reload_completed
   && std_reg_operand (operands[0], QImode)
   && c4x_shiftable_constant (operands[1]) < 0"
  [(set (match_dup 0) (match_dup 2))
   (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 4)))
   (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
  "
{
   /* Generate two's complement value of 16 MSBs.  */
   operands[2] = gen_rtx (CONST_INT, VOIDmode,
			  (((INTVAL (operands[1]) >> 16) & 0xffff)
			   - 0x8000) ^ ~0x7fff);
   operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
   operands[4] = GEN_INT (16);
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))]
  "TARGET_C3X && ! TARGET_SMALL
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && reload_completed
   && std_reg_operand (operands[0], QImode)
   && c4x_shiftable_constant (operands[1]) < 0"
  [(set (match_dup 0) (match_dup 2))
   (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 4)))
   (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
  "
{
   /* Generate two's complement value of 16 MSBs.  */
   operands[2] = gen_rtx (CONST_INT, VOIDmode,
			  (((INTVAL (operands[1]) >> 16) & 0xffff)
			   - 0x8000) ^ ~0x7fff);
   operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
   operands[4] = GEN_INT (16);
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))
   (clobber (reg:QI 16))]
  "TARGET_C3X
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && reload_completed
   && std_reg_operand (operands[0], QImode)
   && c4x_shiftable_constant (operands[1]) >= 0"
  [(set (match_dup 0) (match_dup 2))
   (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 3)))]
  "
{
   /* Generate two's complement value of MSBs.  */
   int shift = c4x_shiftable_constant (operands[1]);

   operands[2] = GEN_INT ((((INTVAL (operands[1]) >> shift) & 0xffff)
			   - 0x8000) ^ ~0x7fff);
   operands[3] = GEN_INT (shift);
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))]
  "TARGET_C3X
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && reload_completed
   && std_reg_operand (operands[0], QImode)
   && c4x_shiftable_constant (operands[1]) >= 0"
  [(set (match_dup 0) (match_dup 2))
   (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 3)))]
  "
{
   /* Generate two's complement value of MSBs.  */
   int shift = c4x_shiftable_constant (operands[1]);

   operands[2] = GEN_INT ((((INTVAL (operands[1]) >> shift) & 0xffff)
			    - 0x8000) ^ ~0x7fff);
   operands[3] = GEN_INT (shift);
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))
   (clobber (reg:QI 16))]
  "! TARGET_SMALL
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && ! IS_HIGH_CONST (INTVAL (operands[1]))
   && reload_completed
   && ! std_reg_operand (operands[0], QImode)"
  [(set (match_dup 2) (high:QI (match_dup 3)))
   (set (match_dup 0) (match_dup 4))
   (use (match_dup 1))]
  "
{
   rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
   operands[2] = dp_reg;
   operands[3] = force_const_mem (Pmode, operands[1]);
   operands[4] = change_address (operands[3], QImode,
			         gen_rtx_LO_SUM (Pmode, dp_reg,
                                                 XEXP (operands[3], 0)));
   operands[3] = XEXP (operands[3], 0);
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))]
  "! TARGET_SMALL
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && ! IS_HIGH_CONST (INTVAL (operands[1]))
   && reload_completed
   && ! std_reg_operand (operands[0], QImode)"
  [(set (match_dup 2) (high:QI (match_dup 3)))
   (set (match_dup 0) (match_dup 4))
   (use (match_dup 1))]
  "
{
   rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
   operands[2] = dp_reg;
   operands[3] = force_const_mem (Pmode, operands[1]);
   operands[4] = change_address (operands[3], QImode,
			         gen_rtx_LO_SUM (Pmode, dp_reg,
                                                 XEXP (operands[3], 0)));
   operands[3] = XEXP (operands[3], 0);
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))
   (clobber (reg:QI 16))]
  "TARGET_SMALL
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && ! IS_HIGH_CONST (INTVAL (operands[1]))
   && reload_completed
   && ((TARGET_C3X && c4x_shiftable_constant (operands[1]) < 0)
       || ! std_reg_operand (operands[0], QImode))"
  [(set (match_dup 0) (match_dup 2))
   (use (match_dup 1))]
  "
{
   rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
   operands[2] = force_const_mem (Pmode, operands[1]);
   operands[2] = change_address (operands[2], QImode,
			         gen_rtx_LO_SUM (Pmode, dp_reg,
                                                 XEXP (operands[2], 0)));
}")

(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
	(match_operand:QI 1 "const_int_operand" ""))]
  "TARGET_SMALL
   && ! IS_INT16_CONST (INTVAL (operands[1]))
   && ! IS_HIGH_CONST (INTVAL (operands[1]))
   && reload_completed
   && ((TARGET_C3X && c4x_shiftable_constant (operands[1]) < 0)
       || ! std_reg_operand (operands[0], QImode))"
  [(set (match_dup 0) (match_dup 2))
   (use (match_dup 1))]
  "
{
   rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
   operands[2] = force_const_mem (Pmode, operands[1]);
   operands[2] = change_address (operands[2], QImode,
			         gen_rtx_LO_SUM (Pmode, dp_reg,
                                                 XEXP (operands[2], 0)));
}")

(define_split
  [(set (match_operand:HI 0 "reg_operand" "")
	(match_operand:HI 1 "const_int_operand" ""))
   (clobber (reg:QI 16))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 5))]
  "
{
   operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
   operands[3] = c4x_operand_subword (operands[0], 1, 1, HImode);
   operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
   operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);
}")


; We need to clobber the DP reg to be safe in case we
; need to load this address from memory
(define_insn "load_immed_address"
  [(set (match_operand:QI 0 "reg_operand" "=a?x?c*r")
        (match_operand:QI 1 "symbolic_address_operand" ""))
   (clobber (reg:QI 16))]
  "TARGET_LOAD_ADDRESS"
  "#"
  [(set_attr "type" "multi")])


(define_split
  [(set (match_operand:QI 0 "std_reg_operand" "")
        (match_operand:QI 1 "symbolic_address_operand" ""))
   (clobber (reg:QI 16))]
  "reload_completed && ! TARGET_C3X && ! TARGET_TI"
  [(set (match_dup 0) (high:QI (match_dup 1)))
   (set (match_dup 0) (lo_sum:QI (match_dup 0) (match_dup 1)))]
  "")

; CC has been selected to load a symbolic address.  We force the address
; into memory and then generate LDP and LDIU insns.
; This is also required for the C30 if we pretend that we can 
; easily load symbolic addresses into a register.
(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
        (match_operand:QI 1 "symbolic_address_operand" ""))
   (clobber (reg:QI 16))]
  "reload_completed
   && ! TARGET_SMALL 
   && (TARGET_C3X || TARGET_TI || ! std_reg_operand (operands[0], QImode))"
  [(set (match_dup 2) (high:QI (match_dup 3)))
   (set (match_dup 0) (match_dup 4))
   (use (match_dup 1))]
  "
{
   rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
   operands[2] = dp_reg;
   operands[3] = force_const_mem (Pmode, operands[1]);
   operands[4] = change_address (operands[3], QImode,
			         gen_rtx_LO_SUM (Pmode, dp_reg,
                                                 XEXP (operands[3], 0)));
   operands[3] = XEXP (operands[3], 0);
}")

; This pattern is similar to the above but does not emit a LDP
; for the small memory model.
(define_split
  [(set (match_operand:QI 0 "reg_operand" "")
        (match_operand:QI 1 "symbolic_address_operand" ""))
   (clobber (reg:QI 16))]
  "reload_completed
   && TARGET_SMALL
   && (TARGET_C3X || TARGET_TI || ! std_reg_operand (operands[0], QImode))"
  [(set (match_dup 0) (match_dup 2))
   (use (match_dup 1))]
  "
{  
   rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
   operands[2] = force_const_mem (Pmode, operands[1]);
   operands[2] = change_address (operands[2], QImode,
			         gen_rtx_LO_SUM (Pmode, dp_reg,
                                                 XEXP (operands[2], 0)));
}")

(define_insn "loadhi_big_constant"
  [(set (match_operand:HI 0 "reg_operand" "=c*d")
        (match_operand:HI 1 "const_int_operand" ""))
   (clobber (reg:QI 16))]
  ""
  "#"
  [(set_attr "type" "multi")])

;
; LDIU/LDA/STI/STIK
;
; The following moves will not set the condition codes register.
;

; This must come before the general case
(define_insn "*movqi_stik"
  [(set (match_operand:QI 0 "memory_operand" "=m")
        (match_operand:QI 1 "stik_const_operand" "K"))]
  "! TARGET_C3X"
  "stik\\t%1,%0"
  [(set_attr "type" "store")])

(define_insn "loadqi_big_constant"
  [(set (match_operand:QI 0 "reg_operand" "=c*d")
        (match_operand:QI 1 "const_int_operand" ""))
   (clobber (reg:QI 16))]
  "! IS_INT16_CONST (INTVAL (operands[1]))
   && ! IS_HIGH_CONST (INTVAL (operands[1]))"
  "#"
  [(set_attr "type" "multi")])

; We must provide an alternative to store to memory in case we have to
; spill a register.
(define_insn "movqi_noclobber"
  [(set (match_operand:QI 0 "dst_operand" "=d,*c,m,r")
        (match_operand:QI 1 "src_hi_operand" "rIm,rIm,r,O"))]
  "(REG_P (operands[0]) || REG_P (operands[1])
    || GET_CODE (operands[0]) == SUBREG
    || GET_CODE (operands[1]) == SUBREG)
    && ! symbolic_address_operand (operands[1], QImode)"
  "*
   if (which_alternative == 2)
     return \"sti\\t%1,%0\";

   if (! TARGET_C3X && which_alternative == 3)
     {
       operands[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff);
       return \"ldhi\\t%1,%0\";
     }

   /* The lda instruction cannot use the same register as source
      and destination.  */
   if (! TARGET_C3X && which_alternative == 1
       && (   IS_ADDR_REG (operands[0])
           || IS_INDEX_REG (operands[0])
           || IS_SP_REG (operands[0]))
       && (REGNO (operands[0]) != REGNO (operands[1])))
      return \"lda\\t%1,%0\";
   return \"ldiu\\t%1,%0\";
  "
  [(set_attr "type" "unary,lda,store,unary")
   (set_attr "data" "int16,int16,int16,high_16")])

;
; LDI
;

; We shouldn't need these peepholes, but the combiner seems to miss them...
(define_peephole
  [(set (match_operand:QI 0 "ext_reg_operand" "=d")
        (match_operand:QI 1 "src_operand" "rIm"))