stormy16.md

linux下的gcc编译器

(define_expand "beq"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (EQ, operands[0]); DONE; }")

(define_expand "bne"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (NE, operands[0]); DONE; }")

(define_expand "bge"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GE, operands[0]); DONE; }")

(define_expand "bgt"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GT, operands[0]); DONE; }")

(define_expand "ble"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LE, operands[0]); DONE; }")

(define_expand "blt"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LT, operands[0]); DONE; }")

(define_expand "bgeu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GEU, operands[0]); DONE; }")

(define_expand "bgtu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GTU, operands[0]); DONE; }")

(define_expand "bleu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LEU, operands[0]); DONE; }")

(define_expand "bltu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LTU, operands[0]); DONE; }")


(define_insn "*cbranchhi"
  [(set (pc) 
	(if_then_else (match_operator:HI 1 "comparison_operator"
				      [(match_operand:HI 2 "nonmemory_operand" 
					"r,e,L")
				       (match_operand:HI 3 "nonmemory_operand"
						      "r,L,e")])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
   (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
  ""
  "*
{
  return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 0, insn);
}"
  [(set_attr "branch_class" "bcc12")
   (set_attr "psw_operand" "0,0,1")])

(define_insn "*cbranchhi_neg"
  [(set (pc) 
	(if_then_else (match_operator:HI 1 "comparison_operator"
				      [(match_operand:HI 2 "nonmemory_operand" 
							 "r,e,L")
				       (match_operand:HI 3 "nonmemory_operand"
							 "r,L,e")])
		      (pc)
		      (label_ref (match_operand 0 "" ""))))
   (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
  ""
  "*
{
  return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 1, insn);
}"
  [(set_attr "branch_class" "bcc12")
   (set_attr "psw_operand" "0,0,1")])

(define_insn "*eqbranchsi"
  [(set (pc)
	(if_then_else (match_operator:SI 1 "equality_operator"
				      [(match_operand:SI 2 "register_operand" 
							 "+r")
				       (const_int 0)])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
;; Although I would greatly like the 'match_dup' in the following line
;; to actually be a register constraint, there is (at the time of writing) no
;; way for reload to insert an output reload on the edges out of a branch.
;; If reload is fixed to use insert_insn_on_edge, this can be changed.
   (clobber (match_dup 2))]
  ""
  "*
{
  return xstormy16_output_cbranch_si (operands[1], \"%l0\", 0, insn);
}"
  [(set_attr "branch_class" "bcc8p2")
   (set_attr "psw_operand" "clobber")])

(define_insn_and_split "*ineqbranchsi"
  [(set (pc)
	(if_then_else (match_operator:SI 1 "xstormy16_ineqsi_operator"
				      [(match_operand:SI 2 "register_operand" 
							 "+r")
				       (match_operand:SI 3 "nonmemory_operand" 
							 "ri")])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
;; Although I would greatly like the 'match_dup' in the following line
;; to actually be a register constraint, there is (at the time of writing) no
;; way for reload to insert an output reload on the edges out of a branch.
;; If reload is fixed to use insert_insn_on_edge, this can be changed,
;; preferably to a 'minus' operand that explains the actual operation, like:
; (set (match_operand 5 "register_operand" "=2")
;      (minus:SI (match_operand 6 "register_operand" "2")
;		 (match_operand 7 "register_operand" "3")))
   (clobber (match_dup 2))
   (clobber (match_operand:BI 4 "" "=&y"))]
  ""
  "#"
  "reload_completed"
  [(pc)]
  "{ xstormy16_split_cbranch (SImode, operands[0], operands[1], operands[2],
			     operands[4]); DONE; }"
  [(set_attr "length" "8")])

(define_insn "*ineqbranch_1"
  [(set (pc)
	(if_then_else (match_operator:HI 5 "xstormy16_ineqsi_operator"
		       [(minus:HI (match_operand:HI 1 "register_operand" 
						    "T,r,r")
			   (zero_extend:HI (match_operand:BI 4
							     "register_operand"
							     "y,y,y")))
			(match_operand:HI 3 "nonmemory_operand" "L,Ir,i")])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
   (set (match_operand:HI 2 "register_operand" "=2,2,2")
	(minus:HI (minus:HI (match_dup 1) (zero_extend:HI (match_dup 4)))
		  (match_dup 3)))
   (clobber (match_operand:BI 6 "" "=y,y,y"))]
  ""
  "*
{
  return xstormy16_output_cbranch_si (operands[5], \"%l0\", 0, insn);
}"
  [(set_attr "branch_class" "bcc8p2,bcc8p2,bcc8p4")
   (set_attr "psw_operand" "2,2,2")])


;; ::::::::::::::::::::
;; ::
;; :: Call and branch instructions
;; ::
;; ::::::::::::::::::::

;; Subroutine call instruction returning no value.  Operand 0 is the function
;; to call; operand 1 is the number of bytes of arguments pushed (in mode
;; `SImode', except it is normally a `const_int'); operand 2 is the number of
;; registers used as operands.

;; On most machines, operand 2 is not actually stored into the RTL pattern.  It
;; is supplied for the sake of some RISC machines which need to put this
;; information into the assembler code; they can put it in the RTL instead of
;; operand 1.

(define_expand "call"
  [(call (match_operand:HI 0 "memory_operand" "m")
	 (match_operand 1 "" ""))
   (use (match_operand 2 "immediate_operand" ""))]
  ""
  "xstormy16_expand_call (NULL_RTX, operands[0], operands[1]); DONE;")

;; Subroutine call instruction returning a value.  Operand 0 is the hard
;; register in which the value is returned.  There are three more operands, the
;; same as the three operands of the `call' instruction (but with numbers
;; increased by one).

;; Subroutines that return `BLKmode' objects use the `call' insn.

(define_expand "call_value"
  [(set (match_operand 0 "register_operand" "=r")
	(call (match_operand:HI 1 "memory_operand" "m")
	      (match_operand:SI 2 "" "")))
	(use (match_operand 3 "immediate_operand" ""))]
  ""
  "xstormy16_expand_call (operands[0], operands[1], operands[2]); DONE;")

(define_insn "*call_internal"
  [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
	 (match_operand 1 "" ""))
   (use (match_operand:HI 2 "nonmemory_operand" "X,z"))]
  ""
  "@
   callf %C0
   call %2,%0"
  [(set_attr "length" "4,2")
   (set_attr "psw_operand" "clobber")])

(define_insn "*call_value_internal"
  [(set (match_operand 3 "register_operand" "=r,r")
        (call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
	      (match_operand 1 "" "")))
   (use (match_operand:HI 2 "nonmemory_operand" "X,z"))]
  ""
  "@
   callf %C0
   call %2,%0"
  [(set_attr "length" "4,2")
   (set_attr "psw_operand" "clobber")])

;; Subroutine return
(define_expand "return"
  [(return)]
  "direct_return()"
  "")

(define_insn "return_internal"
  [(return)]
  ""
  "ret"
  [(set_attr "psw_operand" "nop")])

(define_insn "return_internal_interrupt"
  [(return)
   (unspec_volatile [(const_int 0)] 1)]
  ""
  "iret"
  [(set_attr "psw_operand" "clobber")])

;; Normal unconditional jump
(define_insn "jump"
  [(set (pc) (label_ref (match_operand 0 "" "")))]
  ""
  "*
{
  return xstormy16_output_cbranch_hi (NULL_RTX, \"%l0\", 0, insn);
}"
  [(set_attr "branch_class" "br12")
   (set_attr "psw_operand" "nop")])

;; Indirect jump through a register
(define_expand "indirect_jump"
  [(set (match_dup 1) (const_int 0))
   (parallel [(set (pc) (match_operand:HI 0 "register_operand" "r"))
	      (use (match_dup 1))])]
  ""
  "operands[1] = gen_reg_rtx (HImode);")

(define_insn ""
  [(set (pc) (match_operand:HI 0 "register_operand" "r"))
   (use (match_operand:HI 1 "register_operand" "z"))]
  ""
  "jmp %1,%0"
  [(set_attr "length" "4")
   (set_attr "psw_operand" "nop")])

;; Table-based switch statements.
(define_expand "casesi"
  [(use (match_operand:SI 0 "register_operand" ""))
   (use (match_operand:SI 1 "immediate_operand" ""))
   (use (match_operand:SI 2 "immediate_operand" ""))
   (use (label_ref (match_operand 3 "" "")))
   (use (label_ref (match_operand 4 "" "")))]
  ""
  "
{
  xstormy16_expand_casesi (operands[0], operands[1], operands[2],
			  operands[3], operands[4]);
  DONE;
}")

(define_insn "tablejump_pcrel"
  [(set (pc) (mem:HI (plus:HI (pc) 
			      (match_operand:HI 0 "register_operand" "r"))))
   (use (label_ref:SI (match_operand 1 "" "")))]
  ""
  "br %0"
  [(set_attr "psw_operand" "nop")])


;; ::::::::::::::::::::
;; ::
;; :: Prologue and Epilogue instructions
;; ::
;; ::::::::::::::::::::

;; Called after register allocation to add any instructions needed for
;; the prologue.  Using a prologue insn is favored compared to putting
;; all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro,
;; since it allows the scheduler to intermix instructions with the
;; saves of the caller saved registers.  In some cases, it might be
;; necessary to emit a barrier instruction as the last insn to prevent
;; such scheduling.
(define_expand "prologue"
  [(const_int 1)]
  ""
  "
{
  xstormy16_expand_prologue ();
  DONE;
}")

;; Called after register allocation to add any instructions needed for
;; the epilogue.  Using an epilogue insn is favored compared to putting
;; all of the instructions in the TARGET_ASM_FUNCTION_EPILOGUE macro,
;; since it allows the scheduler to intermix instructions with the
;; restires of the caller saved registers.  In some cases, it might be
;; necessary to emit a barrier instruction as the first insn to
;; prevent such scheduling.
(define_expand "epilogue"
  [(const_int 2)]
  ""
  "
{
  xstormy16_expand_epilogue ();
  DONE;
}")


;; ::::::::::::::::::::
;; ::
;; :: Miscellaneous instructions
;; ::
;; ::::::::::::::::::::

;; No operation, needed in case the user uses -g but not -O.
(define_insn "nop"
  [(const_int 0)]
  ""
  "nop"
  [(set_attr "psw_operand" "nop")])

;; Pseudo instruction that prevents the scheduler from moving code above this
;; point.
(define_insn "blockage"
  [(unspec_volatile [(const_int 0)] 0)]
  ""
  ""
  [(set_attr "length" "0")
   (set_attr "psw_operand" "nop")])