stormy16.md

linux下的gcc编译器

	(minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,0,0")
		  (match_operand:HI 2 "nonmemory_operand" "O,P,L,M,rI,M,i")))
   (clobber (match_scratch:BI 3 "=X,X,&y,&y,&y,&y,&y"))]
  ""
  "@
   dec %0,%o2
   inc %0,%O2
   sub Rx,%2
   add Rx,#%n2
   sub %0,%2
   add %0,#%n2
   sub %0,%2"
  [(set_attr "length" "2,2,2,2,2,2,4")])

(define_insn "subchi4"
  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
	(minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
		  (match_operand:HI 2 "nonmemory_operand" "L,Ir,i")))
   (set (match_operand:BI 3 "register_operand" "=y,y,y") 
        (truncate:BI (lshiftrt:SI (minus:SI (zero_extend:SI (match_dup 1))
					    (zero_extend:SI (match_dup 2)))
				  (const_int 16))))]
  ""
  "@
   sub Rx,%2
   sub %0,%2
   sub %0,%2"
  [(set_attr "length" "2,2,4")])

(define_insn "subchi5"
  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
	(minus:HI (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
			  (zero_extend:HI (match_operand:BI 3 
							    "register_operand"
							    "y,y,y")))
		 (match_operand:HI 2 "nonmemory_operand" "L,Ir,i")))
   (set (match_operand:BI 4 "register_operand" "=y,y,y") 
        (truncate:BI (lshiftrt:SI (minus:SI (minus:SI 
					     (zero_extend:SI (match_dup 1))
					     (zero_extend:SI (match_dup 3)))
					    (zero_extend:SI (match_dup 2)))
				  (const_int 16))))]
  ""
  "@
   sbc Rx,%2
   sbc %0,%2
   sbc %0,%2"
  [(set_attr "length" "2,2,4")])

; Basic multiplication
(define_insn "mulhi3"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(mult:HI (match_operand:HI 1 "register_operand" "%a")
		 (match_operand:HI 2 "register_operand" "c")))
   (clobber (match_scratch:HI 3 "=b"))
   ]
  ""
  "mul"
  [(set_attr "psw_operand" "nop")])

;; Unsigned multiplication producing 64 bit results from 32 bit inputs
; The constraint on operand 0 is 't' because it is actually two regs
; long, and both regs must match the constraint.
(define_insn "umulhisi3"
  [(set (match_operand:SI 0 "register_operand" "=t")
	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%a"))
		 (zero_extend:SI (match_operand:HI 2 "register_operand" "c"))))
   ]
  ""
  "mul"
  [(set_attr "psw_operand" "nop")])

;; Unsigned division giving both quotient and remainder
(define_insn "udivmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(udiv:HI (match_operand:HI 1 "register_operand" "a")
		 (match_operand:HI 2 "register_operand" "c")))
   (set (match_operand:HI 3 "register_operand" "=b")
	(umod:HI (match_dup 1)
		 (match_dup 2)))]
  ""
  "div"
  [(set_attr "psw_operand" "nop")])

;; Signed division giving both quotient and remainder
(define_insn "divmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(div:HI (match_operand:HI 1 "register_operand" "a")
		 (match_operand:HI 2 "register_operand" "c")))
   (set (match_operand:HI 3 "register_operand" "=b")
	(mod:HI (match_dup 1)
		 (match_dup 2)))]
  ""
  "sdiv"
  [(set_attr "psw_operand" "nop")])

;; Signed 32/16 division
(define_insn "sdivlh"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(div:HI (match_operand:SI 2 "register_operand" "t")
		 (match_operand:HI 3 "register_operand" "c")))
   (set (match_operand:HI 1 "register_operand" "=b")
	(mod:HI (match_dup 2)
		 (match_dup 3)))]
  ""
  "sdivlh"
  [(set_attr "psw_operand" "nop")])

;; Unsigned 32/16 division
(define_insn "udivlh"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(udiv:HI (match_operand:SI 2 "register_operand" "t")
		 (match_operand:HI 3 "register_operand" "c")))
   (set (match_operand:HI 1 "register_operand" "=b")
	(umod:HI (match_dup 2)
		 (match_dup 3)))]
  ""
  "divlh"
  [(set_attr "psw_operand" "nop")])

;; Negation

(define_expand "neghi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(not:HI (match_operand:HI 1 "register_operand" "")))
   (parallel [(set (match_dup 0) (plus:HI (match_dup 0) (const_int 1)))
	      (clobber (match_scratch:BI 3 ""))])]
  ""
  "")


;; ::::::::::::::::::::
;; ::
;; :: 16 bit Integer Shifts and Rotates
;; ::
;; ::::::::::::::::::::

;; Arithmetic Shift Left
(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ashift:HI (match_operand:HI 1 "register_operand" "0")
		   (match_operand:HI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "shl %0,%2")

;; Arithmetic Shift Right
(define_insn "ashrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (match_operand:HI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "asr %0,%2")

;; Logical Shift Right
(define_insn "lshrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (match_operand:HI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "shr %0,%2")


;; ::::::::::::::::::::
;; ::
;; :: 16 Bit Integer Logical operations
;; ::
;; ::::::::::::::::::::

;; Logical AND, 16 bit integers
(define_insn "andhi3"
  [(set (match_operand:HI 0 "register_operand" "=T,r,r,r")
	(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
		(match_operand:HI 2 "nonmemory_operand" "L,r,K,i")))]
  ""
  "@
   and Rx,%2
   and %0,%2
   clr1 %0,%B2
   and %0,%2"
  [(set_attr "length" "2,2,2,4")])

;; Inclusive OR, 16 bit integers
(define_insn "iorhi3"
  [(set (match_operand:HI 0 "register_operand" "=T,r,r,r")
	(ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
		(match_operand:HI 2 "nonmemory_operand" "L,r,J,i")))]
  ""
  "@
   or Rx,%2
   or %0,%2
   set1 %0,%B2
   or %0,%2"
  [(set_attr "length" "2,2,2,4")])

;; Exclusive OR, 16 bit integers
(define_insn "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
	(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
		(match_operand:HI 2 "nonmemory_operand" "L,r,i")))]
  ""
  "@
   xor Rx,%2
   xor %0,%2
   xor %0,%2"
  [(set_attr "length" "2,2,4")])

;; One's complement, 16 bit integers
(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(not:HI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "not %0")


;; ::::::::::::::::::::
;; ::
;; :: 32 bit Integer arithmetic
;; ::
;; ::::::::::::::::::::

;; Addition
(define_insn_and_split "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_operand:SI 1 "register_operand" "%0")
		 (match_operand:SI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "#"
  "reload_completed"
  [(pc)]
  "{ xstormy16_expand_arith (SImode, PLUS, operands[0], operands[1],
			    operands[2], operands[3]); DONE; } "
  [(set_attr "length" "4")])

;; Subtraction
(define_insn_and_split "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "0")
		 (match_operand:SI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "#"
  "reload_completed"
  [(pc)]
  "{ xstormy16_expand_arith (SImode, MINUS, operands[0], operands[1],
			    operands[2], operands[3]); DONE; } "
  [(set_attr "length" "4")])

(define_expand "negsi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(neg:SI (match_operand:SI 1 "register_operand" "")))]
  ""
  "{ xstormy16_expand_arith (SImode, NEG, operands[0], const0_rtx,
			    operands[1], gen_reg_rtx (BImode)); DONE; }")

;; ::::::::::::::::::::
;; ::
;; :: 32 bit Integer Shifts and Rotates
;; ::
;; ::::::::::::::::::::

;; Arithmetic Shift Left
(define_expand "ashlsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
		   (ashift:SI (match_operand:SI 1 "register_operand" "")
			      (match_operand:SI 2 "const_int_operand" "")))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  " if (! const_int_operand (operands[2], SImode)) FAIL;
  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")

;; Arithmetic Shift Right
(define_expand "ashrsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
		   (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
			        (match_operand:SI 2 "const_int_operand" "")))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  " if (! const_int_operand (operands[2], SImode)) FAIL;
  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")

;; Logical Shift Right
(define_expand "lshrsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
		   (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
			        (match_operand:SI 2 "const_int_operand" "")))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  " if (! const_int_operand (operands[2], SImode)) FAIL;
  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")

(define_insn "*shiftsi"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(match_operator:SI 5 "shift_operator"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operand:SI 2 "const_int_operand" "U,n")]))
   (clobber (match_operand:BI 3 "register_operand" "=y,y"))
   (clobber (match_operand:HI 4 "" "=X,r"))]
  ""
  "* return xstormy16_output_shift (SImode, GET_CODE (operands[5]), 
				   operands[0], operands[2], operands[4]);"
  [(set_attr "length" "6,10")
   (set_attr "psw_operand" "clobber,clobber")])


;; ::::::::::::::::::::
;; ::
;; :: Comparisons
;; ::
;; ::::::::::::::::::::

;; Note, we store the operands in the comparison insns, and use them later
;; when generating the branch or scc operation.

;; First the routines called by the machine independent part of the compiler
(define_expand "cmphi"
  [(set (cc0)
        (compare (match_operand:HI 0 "register_operand" "")
  		 (match_operand:HI 1 "nonmemory_operand" "")))]
  ""
  "
{
  xstormy16_compare_op0 = operands[0];
  xstormy16_compare_op1 = operands[1];
  DONE;
}")

; There are no real SImode comparisons, but some can be emulated
; by performing a SImode subtract and looking at the condition flags.
(define_expand "cmpsi"
  [(set (cc0)
        (compare (match_operand:SI 0 "register_operand" "")
  		 (match_operand:SI 1 "nonmemory_operand" "")))]
  ""
  "
{
  xstormy16_compare_op0 = operands[0];
  xstormy16_compare_op1 = operands[1];
  DONE;
}")


;; ::::::::::::::::::::
;; ::
;; :: Branches
;; ::
;; ::::::::::::::::::::