m88k.md

linux下的gcc编译器

  [(set (pc)
	(if_then_else
	 (eq (match_operator 0 "relop"
			     [(match_operand:CC 1 "register_operand" "r")
			      (const_int 0)])
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L3 %C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (eq (match_operator 0 "even_relop"
			     [(match_operand:CCEVEN 1 "register_operand" "r")
			      (const_int 0)])
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L3 %C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (eq (match_operator 0 "odd_relop"
			     [(match_operand:CCEVEN 1 "register_operand" "r")
			      (const_int 0)])
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L2 %!%C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn "locate1"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(high:SI (unspec:SI [(label_ref (match_operand 1 "" ""))] 0)))]
  ""
  "or.u %0,%#r0,%#hi16(%1#abdiff)")

(define_insn "locate2"
  [(parallel [(set (reg:SI 1) (pc))
	      (set (match_operand:SI 0 "register_operand" "=r")
		   (lo_sum:SI (match_dup 0)
			      (unspec:SI
			       [(label_ref (match_operand 1 "" ""))] 0)))])]
  ""
  "bsr.n %1\;or %0,%0,%#lo16(%1#abdiff)\\n%1:"
  [(set_attr "length" "2")])

;; SImode move instructions

(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, SImode, 0))
    DONE;
}")

(define_expand "reload_insi"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:SI 1 "general_operand" ""))
   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
  ""
  "
{
  if (emit_move_sequence (operands, SImode, operands[2]))
    DONE;

  /* We don't want the clobber emitted, so handle this ourselves.  */
  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
  DONE;
}")

(define_insn ""
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,x,x,x,m")
	(match_operand:SI 1 "move_operand" "rI,m,rO,J,M,x,r,x,m,x"))]
  "(register_operand (operands[0], SImode)
    || register_operand (operands[1], SImode)
    || operands[1] == const0_rtx)"
  "@
   or %0,%#r0,%1
   %V1ld\\t %0,%1
   %v0st\\t %r1,%0
   subu %0,%#r0,%n1
   set %0,%#r0,%s1
   mov.s %0,%1
   mov.s %0,%1
   mov %0,%1
   %V1ld\\t %0,%1
   %v0st\\t %1,%0"
  [(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
	(match_operand:SI 1 "arith32_operand" "rI,J,L,M,n"))]
  ""
  "@
   or %0,%#r0,%1
   subu %0,%#r0,%n1
   or.u %0,%#r0,%X1
   set %0,%#r0,%s1
   or.u %0,%#r0,%X1\;or %0,%0,%x1"
  [(set_attr "type" "arith,arith,arith,bit,marith")])

;; @@ Why the constraint "in"?  Doesn't `i' include `n'?
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
		   (match_operand:SI 2 "immediate_operand" "in")))]
  ""
  "or %0,%1,%#lo16(%g2)")

;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
;; confuse them with real addresses.
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
		   (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
  ""
  "or %0,%1,%#lo16(%g2)"
  ;; Need to set length for this arith insn because operand2
  ;; is not an "arith_operand".
  [(set_attr "length" "1")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(high:SI (match_operand 1 "" "")))]
  ""
  "or.u %0,%#r0,%#hi16(%g1)")

;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
;; confuse them with real addresses.
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
  ""
  "or.u %0,%#r0,%#hi16(%g1)"
  ;; Need to set length for this arith insn because operand2
  ;; is not an arith_operand.
  [(set_attr "length" "1")])

;; HImode move instructions

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "")
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, HImode, 0))
    DONE;
}")

(define_insn ""
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
	(match_operand:HI 1 "move_operand" "rP,m,rO,N"))]
  "(register_operand (operands[0], HImode)
    || register_operand (operands[1], HImode)
    || operands[1] == const0_rtx)"
  "@
   or %0,%#r0,%h1
   %V1ld.hu\\t %0,%1
   %v0st.h\\t %r1,%0
   subu %0,%#r0,%H1"
  [(set_attr "type" "arith,load,store,arith")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(subreg:HI (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
  "!flag_pic"
  "or %0,%1,%#lo16(%2)")

;; QImode move instructions

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, QImode, 0))
    DONE;
}")

(define_insn ""
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r")
	(match_operand:QI 1 "move_operand" "rP,m,rO,N"))]
  "(register_operand (operands[0], QImode)
    || register_operand (operands[1], QImode)
    || operands[1] == const0_rtx)"
  "@
   or %0,%#r0,%q1
   %V1ld.bu\\t %0,%1
   %v0st.b\\t %r1,%0
   subu %r0,%#r0,%Q1"
  [(set_attr "type" "arith,load,store,arith")])

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
	(subreg:QI (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
  "!flag_pic"
  "or %0,%1,%#lo16(%2)")

;; DImode move instructions

(define_expand "movdi"
  [(set (match_operand:DI 0 "general_operand" "")
	(match_operand:DI 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, DImode, 0))
    DONE;
}")

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=r,x")
	(const_int 0))]
  ""
  "@
   or %0,%#r0,0\;or %d0,%#r0,0
   mov %0,%#x0"
  [(set_attr "type" "marith,mov")])

(define_insn ""
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,x,x,x,m")
	(match_operand:DI 1 "nonimmediate_operand" "r,m,r,x,r,x,m,x"))]
  ""
  "@
   or %0,%#r0,%1\;or %d0,%#r0,%d1
   %V1ld.d\\t %0,%1
   %v0st.d\\t %1,%0
   mov.d %0,%1
   mov.d %0,%1
   mov %0,%1
   %V1ld.d\\t %0,%1
   %v0st.d\\t %1,%0"
  [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=r")
	(subreg:DI (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
  "!flag_pic"
  "or %0,%1,%#lo16(%2)")

(define_insn ""
  [(set (match_operand:DI 0 "register_operand" "=r")
	(match_operand:DI 1 "immediate_operand" "n"))]
   ""
   "* return output_load_const_dimode (operands);"
  [(set_attr "type" "marith")
   (set_attr "length" "4")]) ; length is 2, 3 or 4.

;; DFmode move instructions

(define_expand "movdf"
  [(set (match_operand:DF 0 "general_operand" "")
	(match_operand:DF 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, DFmode, 0))
    DONE;
}")

(define_split
  [(set (match_operand:DF 0 "register_operand" "=r")
	(match_operand:DF 1 "register_operand" "r"))]
  "reload_completed
   && GET_CODE (operands[0]) == REG && !XRF_REGNO_P (REGNO (operands[0]))
   && GET_CODE (operands[1]) == REG && !XRF_REGNO_P (REGNO (operands[1]))"
  [(set (match_dup 2) (match_dup 3))
   (set (match_dup 4) (match_dup 5))]
  "
{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
  operands[3] = operand_subword (operands[1], 0, 0, DFmode);
  operands[4] = operand_subword (operands[0], 1, 0, DFmode);
  operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")

;; @@ This pattern is incomplete and doesn't appear necessary.
;;
;; This pattern forces (set (reg:DF ...) (const_double ...))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general movdf pattern.

;(define_insn ""
;  [(set (match_operand:DF 0 "general_operand" "=r,o")
;	(match_operand:DF 1 "" "G,G"))]
;  "GET_CODE (operands[1]) == CONST_DOUBLE"
;  "*
;{
;  switch (which_alternative)
;    {
;    case 0:
;      return \"or %0,%#r0,0\;or %d0,%#r0,0\";
;    case 1:
;      operands[1] = adjust_address (operands[0], SImode, 4);
;      return \"%v0st\\t %#r0,%0\;st %#r0,%1\";
;    }
;}")

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r,x")
	(const_int 0))]
  ""
  "@
   or %0,%#r0,0\;or %d0,%#r0,0
   mov %0,%#x0"
  [(set_attr "type" "marith,mov")])

(define_insn ""
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m")
	(match_operand:DF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))]
  ""
  "@
   or %0,%#r0,%1\;or %d0,%#r0,%d1
   %V1ld.d\\t %0,%1
   %v0st.d\\t %1,%0
   mov.d %0,%1
   mov.d %0,%1
   mov %0,%1
   %V1ld.d\\t %0,%1
   %v0st.d\\t %1,%0"
  [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r")
	(subreg:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
  "!flag_pic"
  "or %0,%1,%#lo16(%2)")

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=r")
	(match_operand:DF 1 "immediate_operand" "F"))]
   ""
   "* return output_load_const_double (operands);"
  [(set_attr "type" "marith")
   (set_attr "length" "4")]) ; length is 2, 3, or 4.

;; SFmode move instructions

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
  "
{
  if (emit_move_sequence (operands, SFmode, 0))
    DONE;
}")

;; @@ What happens to fconst0_rtx?
(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r,x")
	(const_int 0))]
  ""
  "@
   or %0,%#r0,0
   mov %0,%#x0"
  [(set_attr "type" "arith,mov")])

(define_insn ""
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m")
	(match_operand:SF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))]
  ""
  "@
   or %0,%#r0,%1
   %V1ld\\t %0,%1
   %v0st\\t %r1,%0
   mov.s %0,%1
   mov.s %0,%1
   mov %0,%1
   %V1ld\\t %0,%1
   %v0st\\t %r1,%0"
  [(set_attr "type" "arith,load,store,mov,mov,mov,load,store")])

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r")
	(subreg:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
  "!flag_pic"
  "or %0,%1,%#lo16(%2)")

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=r")
	(match_operand:SF 1 "immediate_operand" "F"))]
  "operands[1] != const0_rtx"
  "* return output_load_const_float (operands);"
  [(set_attr "type" "marith")]) ; length is 1 or 2.

;; String/block move insn.  See m88k.c for details.

(define_expand "movstrsi"
  [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
		   (mem:BLK (match_operand:BLK 1 "" "")))
	      (use (match_operand:SI 2 "arith32_operand" ""))
	      (use (match_operand:SI 3 "immediate_operand" ""))])]
  ""
  "
{
  rtx dest_mem = operands[0];
  rtx src_mem = operands[1];
  operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
  operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
  expand_block_move (dest_mem, src_mem, operands);
  DONE;
}")

;; ??? We shouldn't be allowing such mode mismatches
(define_insn ""
  [(set (match_operand 0 "register_operand" "=r")
	(match_operand:BLK 1