m88k.md

linux下的gcc编译器

  [(set (match_operand:CC 0 "register_operand" "=r,r,r,r")
	(compare:CC (match_operand:DF 1 "register_operand" "r,r,x,x")
		    (match_operand:DF 2 "real_or_0_operand" "r,G,x,G")))]
  ""
  "@
   fcmp.sdd %0,%1,%2
   fcmp.sds %0,%1,%#r0
   fcmp.sdd %0,%1,%2
   fcmp.sds %0,%1,%#x0"
  [(set_attr "type" "dpcmp")])

;; Store condition code insns.  The compare insns set a register
;; rather than cc0 and record that register for use here.  See above
;; for the special treatment of cmpsi with a constant operand.

;; @@ For the m88110, use fcmpu for bxx sxx inequality comparisons.

(define_expand "seq"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (EQ, SImode);")

(define_expand "sne"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (NE, SImode);")

(define_expand "sgt"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GT, SImode);")

(define_expand "sgtu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GTU, SImode);")

(define_expand "slt"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LT, SImode);")

(define_expand "sltu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LTU, SImode);")

(define_expand "sge"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GE, SImode);")

(define_expand "sgeu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (GEU, SImode);")

(define_expand "sle"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LE, SImode);")

(define_expand "sleu"
  [(set (match_operand:SI 0 "register_operand" "")
	(match_dup 1))]
  ""
  "operands[1] = emit_test (LEU, SImode);")

;; The actual set condition code instruction.

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operator:SI 1 "relop"
			   [(match_operand:CC 2 "register_operand" "r")
			    (const_int 0)]))]
  ""
  "ext %0,%2,1<%C1>"
  [(set_attr "type" "bit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operator:SI 1 "even_relop"
			   [(match_operand:CCEVEN 2 "register_operand" "r")
			    (const_int 0)]))]
  ""
  "ext %0,%2,1<%C1>"
  [(set_attr "type" "bit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(not:SI (match_operator:SI 1 "odd_relop"
			   [(match_operand:CCEVEN 2 "register_operand" "r")
			    (const_int 0)])))]
  ""
  "ext %0,%2,1<%!%C1>"
  [(set_attr "type" "bit")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operator:SI 1 "odd_relop"
			   [(match_operand:CCEVEN 2 "register_operand" "r")
			    (const_int 0)]))
   (clobber (match_operand:SI 3 "register_operand" "=r"))]
  ""
  [(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])))
   (set (match_dup 0) (not:SI (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operator:SI 1 "odd_relop"
			   [(match_operand:CCEVEN 2 "register_operand" "r")
			    (const_int 0)]))
   (clobber (match_scratch:SI 3 "=r"))]
  ""
  "#")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI
	 (match_operator:SI 1 "relop"
			    [(match_operand:CC 2 "register_operand" "r")
			     (const_int 0)])))]
  ""
  "extu %0,%2,1<%C1>"
  [(set_attr "type" "bit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI
	 (match_operator:SI 1 "even_relop"
			    [(match_operand:CCEVEN 2 "register_operand" "r")
			     (const_int 0)])))]
  ""
  "extu %0,%2,1<%C1>"
  [(set_attr "type" "bit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI
	 (not:SI (match_operator:SI 1 "odd_relop"
			    [(match_operand:CCEVEN 2 "register_operand" "r")
			     (const_int 0)]))))]
  ""
  "extu %0,%2,1<%!%C1>"
  [(set_attr "type" "bit")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operator:SI 1 "odd_relop"
			   [(match_operand:CCEVEN 2 "register_operand" "r")
			    (const_int 0)])))
   (clobber (match_operand:SI 3 "register_operand" "=r"))]
  ""
  [(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2)
                                                       (const_int 0)]))))
   (set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))]
  "")

(define_insn
 ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operator:SI 1 "odd_relop"
			   [(match_operand:CCEVEN 2 "register_operand" "r")
			    (const_int 0)])))
   (clobber (match_scratch:SI 3 "=r"))]
  ""
  "#")




;; Conditional branch insns.  The compare insns set a register
;; rather than cc0 and record that register for use here.  See above
;; for the special case of cmpsi with a constant operand.

(define_expand "bcnd"
  [(set (pc)
	(if_then_else (match_operand 0 "" "")
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg) abort ();")

(define_expand "bxx"
  [(set (pc)
	(if_then_else (match_operand 0 "" "")
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0) abort ();")

(define_expand "beq"
  [(set (pc)
	(if_then_else (eq (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (EQ, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bne"
  [(set (pc)
	(if_then_else (ne (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (NE, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bgt"
  [(set (pc)
	(if_then_else (gt (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (GT, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bgtu"
  [(set (pc)
	(if_then_else (gtu (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_jump_insn (gen_bxx (emit_test (GTU, VOIDmode), operands[0]));
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "blt"
  [(set (pc)
	(if_then_else (lt (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (LT, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bltu"
  [(set (pc)
	(if_then_else (ltu (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_jump_insn (gen_bxx (emit_test (LTU, VOIDmode), operands[0]));
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bge"
  [(set (pc)
	(if_then_else (ge (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (GE, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bgeu"
  [(set (pc)
	(if_then_else (geu (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_jump_insn (gen_bxx (emit_test (GEU, VOIDmode), operands[0]));
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "ble"
  [(set (pc)
	(if_then_else (le (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_bcnd (LE, operands[0]);
       DONE;
     }
   operands[1] = m88k_compare_reg;")

(define_expand "bleu"
  [(set (pc)
	(if_then_else (leu (match_dup 1) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "if (m88k_compare_reg == 0)
     {
       emit_jump_insn (gen_bxx (emit_test (LEU, VOIDmode), operands[0]));
       DONE;
     }
   operands[1] = m88k_compare_reg;")

;; The actual conditional branch instruction (both directions).  This
;; uses two unusual template patterns, %Rx and %Px.  %Rx is a prefix code
;; for the immediately following condition and reverses the condition iff
;; operand `x' is a LABEL_REF.  %Px does nothing if `x' is PC and outputs
;; the operand if `x' is a LABEL_REF.

(define_insn ""
  [(set (pc) (if_then_else
	      (match_operator 0 "relop"
			      [(match_operand:CC 1 "register_operand" "r")
			       (const_int 0)])
	      (match_operand 2 "pc_or_label_ref" "")
	      (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "*
{
  if (mostly_false_jump (insn, operands[0]))
    return \"bb0%. %R2%C0,%1,%P2%P3\";
  else
    return \"bb1%. %R3%C0,%1,%P2%P3\";
}"
  [(set_attr "type" "branch")])

;;
;; Here branch prediction is sacrificed. To get it back, you need 
;;  - CCODD (CC mode where the ODD bits are valid)
;;  - several define_split that can apply De Morgan's Law.
;;  - transformations between CCEVEN and CCODD modes. 
;;  

(define_insn ""
  [(set (pc) (if_then_else
	      (match_operator 0 "even_relop"
			      [(match_operand:CCEVEN 1 "register_operand" "r")
			       (const_int 0)])
	      (match_operand 2 "pc_or_label_ref" "")
	      (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L2%. %C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc) (if_then_else
	      (match_operator 0 "odd_relop"
			      [(match_operand:CCEVEN 1 "register_operand" "r")
			       (const_int 0)])
	      (match_operand 2 "pc_or_label_ref" "")
	      (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L3%. %!%C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

;; Branch conditional on scc values.  These arise from manipulations on
;; compare words above.
;; Are these really used ? 

(define_insn ""
  [(set (pc)
	(if_then_else
	 (ne (match_operator 0 "relop"
			     [(match_operand:CC 1 "register_operand" "r")
			      (const_int 0)])
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L2 %C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (ne (match_operator 0 "even_relop"
			     [(match_operand:CCEVEN 1 "register_operand" "r")
			      (const_int 0)])
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L2 %C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""
  [(set (pc)
	(if_then_else
	 (ne (match_operator 0 "odd_relop"
			     [(match_operand:CCEVEN 1 "register_operand" "r")
			      (const_int 0)])
	     (const_int 0))
	 (match_operand 2 "pc_or_label_ref" "")
	 (match_operand 3 "pc_or_label_ref" "")))]
  ""
  "bb%L3 %!%C0,%1,%P2%P3"
  [(set_attr "type" "branch")])

(define_insn ""