m88k.md

linux下的gcc编译器

  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
     ; /* The conditions match.  */
   else if (GET_CODE (operands[1])
	    == reverse_condition (GET_CODE (operands[3])))
     /* Reverse the condition by complementing the compare word.  */
     operands[4] = gen_rtx_NOT (CCmode, operands[4]);
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);

       operands[4] = gen_rtx_ROTATE (CCmode, operands[4],
				     GEN_INT (((cv2 & ~1) - (cv1 & ~1))
					      & 0x1f));
       /* Reverse the condition if needed.  */
       if ((cv1 & 1) != (cv2 & 1))
	 operands[4] = gen_rtx_NOT (CCmode, operands[4]);
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (neg:SI 
		 (match_operator 1 "odd_relop"
				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
				  (const_int 0)]))
		(neg:SI
		 (match_operator 3 "odd_relop"
				 [(match_operand 4 "partial_ccmode_register_operand" "r")
				  (const_int 0)]))))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  ""
  [(set (match_dup 5)
	(and:CCEVEN (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
     ; /* The conditions match.  */
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);

       operands[4] = gen_rtx_ROTATE (CCmode, operands[4],
				     GEN_INT ((cv2 - cv1) & 0x1f));
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (neg:SI 
		 (match_operator 1 "odd_relop"
				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
				  (const_int 0)]))
		(neg:SI
		 (match_operator 3 "even_relop"
				 [(match_operand 4 "partial_ccmode_register_operand" "r")
				  (const_int 0)]))))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  ""
  [(set (match_dup 5)
	(ior:CCEVEN (not:CC (match_dup 2))
		(match_dup 4)))
   (set (match_dup 0)
	(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
  if (GET_CODE (operands[1])
	    == reverse_condition (GET_CODE (operands[3])))
     ; 
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);

       operands[2] = gen_rtx_ROTATE (CCmode, operands[2],
				     GEN_INT (((cv1 & ~1) - (cv2 & ~1))
					      & 0x1f));
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operator 1 "even_relop"
				[(match_operand 2 "partial_ccmode_register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "relop"
				[(match_operand 4 "partial_ccmode_register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == GET_CODE (operands[3])
   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
  [(set (match_dup 5)
	(ior:CCEVEN (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
   /* Reverse the condition by complementing the compare word.  */
   if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
      operands[4] = gen_rtx_NOT (CCmode, operands[4]);")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operator 1 "odd_relop"
				[(match_operand 2 "partial_ccmode_register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "odd_relop"
				[(match_operand 4 "partial_ccmode_register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
  [(set (match_dup 5)
	(and:CCEVEN (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operator 1 "odd_relop"
				[(match_operand 2 "partial_ccmode_register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "even_relop"
				[(match_operand 4 "partial_ccmode_register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
  [(set (match_dup 5)
	(ior:CCEVEN (not:CC (match_dup 4))
		(match_dup 2)))
   (set (match_dup 0)
	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (neg:SI 
		 (match_operator 1 "even_relop"
				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
				  (const_int 0)]))
		(neg:SI
		 (match_operator 3 "relop"
				 [(match_operand 4 "partial_ccmode_register_operand" "r")
				  (const_int 0)]))))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  ""
  [(set (match_dup 5)
	(and:CCEVEN (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
     ; /* The conditions match.  */
   else if (GET_CODE (operands[1])
	    == reverse_condition (GET_CODE (operands[3])))
     /* Reverse the condition by complementing the compare word.  */
     operands[4] = gen_rtx_NOT (CCmode, operands[4]);
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);
       operands[4] = gen_rtx_ROTATE (CCmode, operands[4],
				     GEN_INT (((cv2 & ~1) - (cv1 & ~1))
					      & 0x1f));
       /* Reverse the condition if needed.  */
       if ((cv1 & 1) != (cv2 & 1))
	 operands[4] = gen_rtx_NOT (CCmode, operands[4]);
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (neg:SI 
		 (match_operator 1 "odd_relop"
				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
				  (const_int 0)]))
		(neg:SI
		 (match_operator 3 "odd_relop"
				 [(match_operand 4 "partial_ccmode_register_operand" "r")
				  (const_int 0)]))))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  ""
  [(set (match_dup 5)
	(ior:CCEVEN (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
     ; /* The conditions match.  */
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);
       operands[4] = gen_rtx_ROTATE (CCmode, operands[4],
				     GEN_INT ((cv2 - cv1) & 0x1f));
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (neg:SI 
		 (match_operator 1 "odd_relop"
				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
				  (const_int 0)]))
		(neg:SI
		 (match_operator 3 "even_relop"
				 [(match_operand 4 "partial_ccmode_register_operand" "r")
				  (const_int 0)]))))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  ""
  [(set (match_dup 5)
	(and:CCEVEN (not:CC (match_dup 2))
		(match_dup 4)))
   (set (match_dup 0)
	(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
   if (GET_CODE (operands[1])
	    == reverse_condition (GET_CODE (operands[3])))
	;
   else
     {
       /* Make the condition pairs line up by rotating the compare word.  */
       int cv1 = condition_value (operands[1]);
       int cv2 = condition_value (operands[3]);
       operands[2] = gen_rtx_ROTATE (CCmode, operands[2],
				     GEN_INT (((cv1 & ~1) - (cv2 & ~1))
					      & 0x1f));
     }")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operator 1 "even_relop"
				[(match_operand 2 "partial_ccmode_register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "relop"
				[(match_operand 4 "partial_ccmode_register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == GET_CODE (operands[3])
   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
  [(set (match_dup 5)
	(and:CCEVEN (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);
   /* Reverse the condition by complementing the compare word.  */
   if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
      operands[4] = gen_rtx_NOT (CCmode, operands[4]);")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operator 1 "odd_relop"
				[(match_operand 2 "partial_ccmode_register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "odd_relop"
				[(match_operand 4 "partial_ccmode_register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
  [(set (match_dup 5)
	(ior:CCEVEN (match_dup 4)
		(match_dup 2)))
   (set (match_dup 0)
	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);")

(define_split
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operator 1 "odd_relop"
				[(match_operand 2 "partial_ccmode_register_operand" "%r")
				 (const_int 0)])
		(match_operator 3 "even_relop"
				[(match_operand 4 "partial_ccmode_register_operand" "r")
				 (const_int 0)])))
   (clobber (match_operand:SI 5 "register_operand" "=r"))]
  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
  [(set (match_dup 5)
	(and:CCEVEN (not:CC (match_dup 2))
		(match_dup 4)))
   (set (match_dup 0)
	(match_op_dup 3 [(match_dup 5) (const_int 0)]))]
  "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);")


;; Logical operations on compare words.

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(and:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
		(match_operand 2 "partial_ccmode_register_operand" "r")))]
  ""
  "and.c %0,%2,%1")

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(and:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
		(match_operand 2 "partial_ccmode_register_operand" "r")))]
  ""
  "and %0,%1,%2")

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(ior:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
		(match_operand 2 "partial_ccmode_register_operand" "r")))]
  ""
  "or.c %0,%2,%1")

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(ior:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
		(match_operand 2 "partial_ccmode_register_operand" "r")))]
  ""
  "or %0,%1,%2")

(define_insn ""
  [(set (match_operand:CC 0 "register_operand" "=r")
	(rotate:CC (match_operand:CC 1 "register_operand" "r")
		   (match_operand:CC 2 "int5_operand" "")))]
  ""
  "rot %0,%1,%2"
  [(set_attr "type" "bit")])

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(rotate:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "r")
		   (match_operand:CC 2 "int5_operand" "")))]
  ""
  "rot %0,%1,%2"
  [(set_attr "type" "bit")])

;; rotate/and[.c] and rotate/ior[.c]

(define_split
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(ior:CCEVEN (match_dup 4) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_scratch:CCEVEN 4 "=r"))]
  ""
  "#")

(define_split
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(ior:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_scratch:CCEVEN 4 "=r"))]
  ""
  "#")

(define_split
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(and:CCEVEN (match_dup 4) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
			   (match_operand:CC 2 "int5_operand" ""))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_scratch:CCEVEN 4 "=r"))]
  ""
  "#")

(define_split
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
  ""
  [(set (match_dup 4)
	(rotate:CC (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(and:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
  "")

(define_insn ""
  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
				   (match_operand:CC 2 "int5_operand" "")))
		(match_operand 3 "partial_ccmode_register_operand" "r")))
   (clobber (match_scratch:CCEVEN 4 "=r"))]
  ""
  "#")