m88k.h

linux下的gcc编译器

#ifndef REG_OK_STRICT

/* Nonzero if X is a hard reg that can be used as an index
   or if it is a pseudo reg.  Not the argument pointer.  */
#define REG_OK_FOR_INDEX_P(X)                                         \
  (!XRF_REGNO_P(REGNO (X)))
/* Nonzero if X is a hard reg that can be used as a base reg
   or if it is a pseudo reg.  */
#define REG_OK_FOR_BASE_P(X) (REG_OK_FOR_INDEX_P (X))

#else

/* Nonzero if X is a hard reg that can be used as an index.  */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as a base reg.  */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))

#endif

/* Try machine-dependent ways of modifying an illegitimate address
   to be legitimate.  If we find one, return the new, valid address.
   This macro is used in only one place: `memory_address' in explow.c.

   OLDX is the address as it was before break_out_memory_refs was called.
   In some cases it is useful to look at this to decide what needs to be done.

   MODE and WIN are passed so that this macro can use
   GO_IF_LEGITIMATE_ADDRESS.

   It is always safe for this macro to do nothing.  It exists to recognize
   opportunities to optimize the output.  */

/* On the m88000, change REG+N into REG+REG, and REG+(X*Y) into REG+REG.  */

#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
{								\
  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
    (X) = gen_rtx_PLUS (SImode, XEXP (X, 0),			\
			copy_to_mode_reg (SImode, XEXP (X, 1))); \
  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0)))	\
    (X) = gen_rtx_PLUS (SImode, XEXP (X, 1),			\
			copy_to_mode_reg (SImode, XEXP (X, 0))); \
  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)	\
    (X) = gen_rtx_PLUS (SImode, XEXP (X, 1),			\
			force_operand (XEXP (X, 0), 0));	\
  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)	\
    (X) = gen_rtx_PLUS (SImode, XEXP (X, 0),			\
			force_operand (XEXP (X, 1), 0));	\
  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS)	\
    (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
			XEXP (X, 1));				\
  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS)	\
    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),			\
			force_operand (XEXP (X, 1), NULL_RTX));	\
  if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST	\
	   || GET_CODE (X) == LABEL_REF)			\
    (X) = legitimize_address (flag_pic, X, 0, 0);		\
  if (memory_address_p (MODE, X))				\
    goto WIN; }

/* Go to LABEL if ADDR (a legitimate address expression)
   has an effect that depends on the machine mode it is used for.
   On the m88000 this is never true.  */

#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)

/* Nonzero if the constant value X is a legitimate general operand.
   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
#define LEGITIMATE_CONSTANT_P(X) (1)

/* Define this, so that when PIC, reload won't try to reload invalid
   addresses which require two reload registers.  */

#define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))


/*** Condition Code Information ***/

/* C code for a data type which is used for declaring the `mdep'
   component of `cc_status'.  It defaults to `int'.  */
/* #define CC_STATUS_MDEP int */

/* A C expression to initialize the `mdep' field to "empty".  */
/* #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) */

/* Macro to zap the normal portions of CC_STATUS, but leave the
   machine dependent parts (ie, literal synthesis) alone.  */
/* #define CC_STATUS_INIT_NO_MDEP \
  (cc_status.flags = 0, cc_status.value1 = 0, cc_status.value2 = 0) */

/* When using a register to hold the condition codes, the cc_status
   mechanism cannot be used.  */
#define NOTICE_UPDATE_CC(EXP, INSN) (0)

/*** Miscellaneous Parameters ***/

/* Define the codes that are matched by predicates in m88k.c.  */
#define PREDICATE_CODES	  						\
  {"move_operand", {SUBREG, REG, CONST_INT, LO_SUM, MEM}},		\
  {"call_address_operand", {SUBREG, REG, SYMBOL_REF, LABEL_REF, CONST}}, \
  {"arith_operand", {SUBREG, REG, CONST_INT}},				\
  {"arith5_operand", {SUBREG, REG, CONST_INT}},				\
  {"arith32_operand", {SUBREG, REG, CONST_INT}},			\
  {"arith64_operand", {SUBREG, REG, CONST_INT}},			\
  {"int5_operand", {CONST_INT}},					\
  {"int32_operand", {CONST_INT}},					\
  {"add_operand", {SUBREG, REG, CONST_INT}},				\
  {"reg_or_bbx_mask_operand", {SUBREG, REG, CONST_INT}},		\
  {"real_or_0_operand", {SUBREG, REG, CONST_DOUBLE}},			\
  {"reg_or_0_operand", {SUBREG, REG, CONST_INT}},                       \
  {"relop", {EQ, NE, LT, LE, GE, GT, LTU, LEU, GEU, GTU}},		\
  {"even_relop", {EQ, LT, GT, LTU, GTU}},		\
  {"odd_relop", { NE, LE, GE, LEU, GEU}},		\
  {"partial_ccmode_register_operand", { SUBREG, REG}},			\
  {"relop_no_unsigned", {EQ, NE, LT, LE, GE, GT}},			\
  {"equality_op", {EQ, NE}},						\
  {"pc_or_label_ref", {PC, LABEL_REF}},

/* A list of predicates that do special things with modes, and so
   should not elicit warnings for VOIDmode match_operand.  */

#define SPECIAL_MODE_PREDICATES		\
  "partial_ccmode_register_operand",	\
  "pc_or_label_ref",

/* The case table contains either words or branch instructions.  This says
   which.  We always claim that the vector is PC-relative.  It is position
   independent when -fpic is used.  */
#define CASE_VECTOR_INSNS (TARGET_88100 || flag_pic)

/* An alias for a machine mode name.  This is the machine mode that
   elements of a jump-table should have.  */
#define CASE_VECTOR_MODE SImode

/* Define as C expression which evaluates to nonzero if the tablejump
   instruction expects the table to contain offsets from the address of the
   table.
   Do not define this if the table should contain absolute addresses. */
#define CASE_VECTOR_PC_RELATIVE 1

/* Define this if control falls through a `case' insn when the index
   value is out of range.  This means the specified default-label is
   actually ignored by the `case' insn proper.  */
/* #define CASE_DROPS_THROUGH */

/* Define this to be the smallest number of different values for which it
   is best to use a jump-table instead of a tree of conditional branches.
   The default is 4 for machines with a casesi instruction and 5 otherwise.
   The best 88110 number is around 7, though the exact number isn't yet
   known.  A third alternative for the 88110 is to use a binary tree of
   bb1 instructions on bits 2/1/0 if the range is dense.  This may not
   win very much though.  */
#define CASE_VALUES_THRESHOLD (TARGET_88100 ? 4 : 7)

/* Define this as 1 if `char' should by default be signed; else as 0.  */
#define DEFAULT_SIGNED_CHAR 1

/* The 88open ABI says size_t is unsigned int.  */
#define SIZE_TYPE "unsigned int"

/* Handle #pragma pack and sometimes #pragma weak.  */
#define HANDLE_SYSV_PRAGMA 1

/* Tell when to handle #pragma weak.  This is only done for V.4.  */
#define SUPPORTS_WEAK TARGET_SVR4
#define SUPPORTS_ONE_ONLY TARGET_SVR4

/* Max number of bytes we can move from memory to memory
   in one reasonably fast instruction.  */
#define MOVE_MAX 8

/* Define if normal loads of shorter-than-word items from memory clears
   the rest of the bigs in the register.  */
#define BYTE_LOADS_ZERO_EXTEND

/* Zero if access to memory by bytes is faster.  */
#define SLOW_BYTE_ACCESS 1

/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
   is done just by pretending it is already truncated.  */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1

/* Define this if addresses of constant functions
   shouldn't be put through pseudo regs where they can be cse'd.
   Desirable on machines where ordinary constants are expensive
   but a CALL with constant address is cheap.  */
#define NO_FUNCTION_CSE

/* Define this macro if an argument declared as `char' or
   `short' in a prototype should actually be passed as an
   `int'.  In addition to avoiding errors in certain cases of
   mismatch, it also makes for better code on certain machines.  */
#define PROMOTE_PROTOTYPES 1

/* We assume that the store-condition-codes instructions store 0 for false
   and some other value for true.  This is the value stored for true.  */
#define STORE_FLAG_VALUE (-1)

/* Specify the machine mode that pointers have.
   After generation of rtl, the compiler makes no further distinction
   between pointers and any other objects of this machine mode.  */
#define Pmode SImode

/* A function address in a call instruction
   is a word address (for indexing purposes)
   so give the MEM rtx word mode.  */
#define FUNCTION_MODE SImode

/* A barrier will be aligned so account for the possible expansion.
   A volatile load may be preceded by a serializing instruction.
   Account for profiling code output at NOTE_INSN_PROLOGUE_END.
   Account for block profiling code at basic block boundaries.  */
#define ADJUST_INSN_LENGTH(RTX, LENGTH)					\
  if (GET_CODE (RTX) == BARRIER						\
      || (TARGET_SERIALIZE_VOLATILE					\
	  && GET_CODE (RTX) == INSN					\
	  && GET_CODE (PATTERN (RTX)) == SET				\
	  && ((GET_CODE (SET_SRC (PATTERN (RTX))) == MEM		\
	       && MEM_VOLATILE_P (SET_SRC (PATTERN (RTX)))))))		\
    LENGTH += 1;							\
  else if (GET_CODE (RTX) == NOTE					\
	   && NOTE_LINE_NUMBER (RTX) == NOTE_INSN_PROLOGUE_END)		\
    {									\
      if (current_function_profile)					\
	LENGTH += (FUNCTION_PROFILER_LENGTH + REG_PUSH_LENGTH		\
		   + REG_POP_LENGTH);					\
    }									\

/* Track the state of the last volatile memory reference.  Clear the
   state with CC_STATUS_INIT for now.  */
#define CC_STATUS_INIT m88k_volatile_code = '\0'

/* Compute the cost of computing a constant rtl expression RTX
   whose rtx-code is CODE.  The body of this macro is a portion
   of a switch statement.  If the code is computed here,
   return it with a return statement.  Otherwise, break from the switch.

   We assume that any 16 bit integer can easily be recreated, so we
   indicate 0 cost, in an attempt to get GCC not to optimize things
   like comparison against a constant.

   The cost of CONST_DOUBLE is zero (if it can be placed in an insn, it
   is as good as a register; since it can't be placed in any insn, it
   won't do anything in cse, but it will cause expand_binop to pass the
   constant to the define_expands).  */
#define CONST_COSTS(RTX,CODE,OUTER_CODE)		\
  case CONST_INT:					\
    if (SMALL_INT (RTX))				\
      return 0;						\
    else if (SMALL_INTVAL (- INTVAL (RTX)))		\
      return 2;						\
    else if (classify_integer (SImode, INTVAL (RTX)) != m88k_oru_or) \
      return 4;						\
    return 7;						\
  case HIGH:						\
    return 2;						\
  case CONST:						\
  case LABEL_REF:					\
  case SYMBOL_REF:					\
    if (flag_pic)					\
      return (flag_pic == 2) ? 11 : 8;			\
    return 5;						\
  case CONST_DOUBLE:					\
    return 0;

/* Provide the costs of an addressing mode that contains ADDR.
   If ADDR is not a valid address, its cost is irrelevant.
   REG+REG is made slightly more expensive because it might keep
   a register live for longer than we might like.  */
#define ADDRESS_COST(ADDR)				\
  (GET_CODE (ADDR) == REG ? 1 :				\
   GET_CODE (ADDR) == LO_SUM ? 1 :			\
   GET_CODE (ADDR) == HIGH ? 2 :			\
   GET_CODE (ADDR) == MULT ? 1 :			\
   GET_CODE (ADDR) != PLUS ? 4 :			\
   (REG_P (XEXP (ADDR, 0)) && REG_P (XEXP (ADDR, 1))) ? 2 : 1)

/* Provide the costs of a rtl expression.  This is in the body of a
   switch on CODE.  */
#define RTX_COSTS(X,CODE,OUTER_CODE)				\
  case MEM:						\
    return COSTS_N_INSNS (2);				\
  case MULT:						\
    return COSTS_N_INSNS (3);				\
  case DIV:						\
  case UDIV:						\
  case MOD:						\
  case UMOD:						\
    return COSTS_N_INSNS (38);

/* A C expressions returning the cost of moving data of MODE from a register
   to or from memory.  This is more costly than between registers.  */
#define MEMORY_MOVE_COST(MODE,CLASS,IN) 4

/* Provide the cost of a branch.  Exact meaning under development.  */
#define BRANCH_COST (TARGET_88100 ? 1 : 2)

/* Do not break .stabs pseudos into continuations.  */
#define DBX_CONTIN_LENGTH 0

/*** Output of Assembler Code ***/

/* Control the assembler format that we output.  */

/* A C string constant describing how to begin a comment in the target
   assembler language.  The compiler assumes that the comment will end at
   the end of the line.  */
#define ASM_COMMENT_START ";"

/* Allow pseudo-ops to be overridden.  Override these in svr[34].h.  */
#undef	ASCII_DATA_ASM_OP
#undef	READONLY_DATA_SECTION_ASM_OP
#undef	CTORS_SECTION_ASM_OP
#undef	DTORS_SECTION_ASM_OP
#undef  TARGET_ASM_NAMED_SECTION
#undef	INIT_SECTION_ASM_OP
#undef	FINI_SECTION_ASM_OP
#undef	TYPE_AS