m68hc11.md

linux下的gcc编译器

   if (reg_mentioned_p (gen_rtx (REG, HImode, HARD_X_REGNUM), operands[1]))
     {
	emit_insn (gen_zero_extendqihi2 (m68hc11_gen_lowpart (HImode,
							      operands[0]),
					 operands[1]));
	emit_move_insn (gen_rtx (REG, HImode, HARD_X_REGNUM), const0_rtx);
	DONE;
     }
   operands[4] = m68hc11_gen_highpart (HImode, operands[0]);
   operands[5] = m68hc11_gen_lowpart (HImode, operands[0]);
   if (A_REG_P (operands[1]))
     {
       operands[2] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM);
       operands[3] = gen_rtx (REG, HImode, REGNO (operands[1]));
       operands[6] = gen_rtx (REG, QImode, SOFT_TMP_REGNUM);
     }
   else
     {
       operands[5] = operands[2] =
       operands[3] = gen_rtx (REG, HImode, HARD_D_REGNUM);
       operands[6] = operands[1];
     }
")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "non_push_operand" "=dm,d,*A,!*u,d,m,!*u")
	(zero_extend:HI 
	    (match_operand:QI 1 "nonimmediate_operand" "d,*A,d*Am,d,!um,*A,*A")))]
  ""
 "*
{
  if (A_REG_P (operands[0]))
    return \"#\";

  if (H_REG_P (operands[0]))
    {
      output_asm_insn (\"clra\", operands);
      if (operands[0] != operands[1]
          && !(D_REG_P (operands[0]) && D_REG_P (operands[1])))
        {
          if (X_REG_P (operands[1])
	      || (D_REG_P (operands[1]) && X_REG_P (operands[0])))
	    {
	      output_asm_insn (\"stx\\t%t1\", operands);
	      output_asm_insn (\"ldab\\t%T0\", operands);
	    }
	  else if (Y_REG_P (operands[1])
		   || (D_REG_P (operands[1]) && Y_REG_P (operands[0])))
	    {
	      output_asm_insn (\"sty\\t%t1\", operands);
	      output_asm_insn (\"ldab\\t%T0\", operands);
	    }
          else
            {
	      output_asm_insn (\"ldab\\t%b1\", operands);
            }
	  cc_status.flags |= CC_NOT_NEGATIVE;
        }
      else
	{
	  /* Status refers to the clra insn. Status is ok for others
	   * since we have loaded the value in B.
	   */
	  CC_STATUS_INIT;
	}
      return \"\";
    }

  if (A_REG_P (operands[1]))
    {
      output_asm_insn (\"st%1\\t%0\", operands);
      output_asm_insn (\"clr\\t%h0\", operands);
      CC_STATUS_INIT;
    }
  else
    {
      output_asm_insn (\"clr\\t%h0\", operands);
      output_asm_insn (\"stab\\t%b0\", operands);
      cc_status.flags |= CC_NOT_NEGATIVE;
    }

  return \"\";
}")


;;--------------------------------------------------------------------
;;-  Sign extension insns.
;;--------------------------------------------------------------------

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=D,m,u")
	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dmux,d,d")))]
  ""
  "*
{
  rtx ops[3];
  int need_tst = 0;

  /* The 68HC12 has a sign-extension instruction.  Use it when the
     destination is the register (X,D).  First sign-extend the low
     part and fill X with the sign-extension of the high part.  */
  if (TARGET_M6812 && X_REG_P (operands[0]))
    {
      if (!D_REG_P (operands[1]))
        {
	  ops[0] = gen_rtx (REG, QImode, HARD_D_REGNUM);
	  ops[1] = operands[1];
	  m68hc11_gen_movqi (insn, ops);
	}
      return \"sex\\tb,d\\n\\tsex\\ta,x\";
    }

  ops[2] = gen_label_rtx ();

  if (X_REG_P (operands[1]))
    {
      output_asm_insn (\"xgdx\", operands);
      need_tst = 1;
    }
  else if (X_REG_P (operands[0]))
    {
      /* X can be used as an indexed addressing in the source.
         Get the value before clearing it.  */
      if (reg_mentioned_p (ix_reg, operands[1]))
        {
          output_asm_insn (\"ldab\\t%b1\", operands);
	  need_tst = 1;
        }
      output_asm_insn (\"ldx\\t#0\", operands);
    }

  output_asm_insn (\"clra\", operands);
  if (!X_REG_P (operands[0]))
    {
      ops[0] = m68hc11_gen_lowpart (HImode, operands[0]);
      ops[1] = m68hc11_gen_lowpart (QImode, ops[0]);

      if (IS_STACK_PUSH (operands[0]))
        {
          output_asm_insn (\"pshb\", ops);
          output_asm_insn (\"tstb\", ops);
        }
      else
        {
          output_asm_insn (\"stab\\t%b1\", ops);
        }
    }
  else if (D_REG_P (operands[1]) || need_tst)
    {
      output_asm_insn (\"tstb\", operands);
    }
  else
    {
      output_asm_insn (\"ldab\\t%b1\", operands);
    }
  output_asm_insn (\"bpl\\t%l2\", ops);
  output_asm_insn (\"deca\", operands);
  if (X_REG_P (operands[0]))
    output_asm_insn (\"dex\", operands);

  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[2]));

  if (!X_REG_P (operands[0]))
    {
      if (IS_STACK_PUSH (operands[0]))
	{
	  output_asm_insn (\"psha\", ops);
	  output_asm_insn (\"psha\", ops);
	  output_asm_insn (\"psha\", ops);
	}
      else
	{
	  output_asm_insn (\"staa\\t%h0\", ops);

	  ops[0] = m68hc11_gen_highpart (HImode, operands[0]);
	  if (dead_register_here (insn, d_reg))
	    {
	      output_asm_insn (\"tab\", ops);
	      output_asm_insn (\"std\\t%0\", ops);
	    }
	  else
	    {
	      output_asm_insn (\"staa\\t%b0\", ops);
	      output_asm_insn (\"staa\\t%h0\", ops);
	    }
	}
    }

  CC_STATUS_INIT;
  return \"\";
}")


(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "non_push_operand" "=d,*x*ym,u")
	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "dum,0,0")))]
  ""
  "*
{
  rtx ops[2];

  if (A_REG_P (operands[0]))
    return \"#\";

  ops[0] = gen_label_rtx ();
  if (D_REG_P (operands[0]))
    {
      if (TARGET_M6812)
	{
	  if (!D_REG_P (operands[1]))
	    {
	      ops[0] = gen_rtx (REG, QImode, HARD_D_REGNUM);
	      ops[1] = operands[1];
	      m68hc11_gen_movqi (insn, ops);
	    }
	  return \"sex\\tb,d\";
	}
      output_asm_insn (\"clra\", operands);
      if (H_REG_P (operands[1]))
        {
          output_asm_insn (\"tstb\", operands);
        }
      else
        {
	  output_asm_insn (\"ldab\\t%b1\", operands);
        }
      output_asm_insn (\"bpl\\t%l0\", ops);
      output_asm_insn (\"deca\", operands);

      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 
				 CODE_LABEL_NUMBER (ops[0]));
    }
   else
    {
      output_asm_insn (\"clr\\t%h0\", operands);
      if (m68hc11_register_indirect_p (operands[1], HImode))
        {
	  ops[1] = operands[1];
          output_asm_insn (\"brclr\\t%b1 #0x80 %l0\", ops);
	  CC_STATUS_INIT;
        }
      else
        {
          output_asm_insn (\"tst\\t%b1\", operands);
	  output_asm_insn (\"bpl\\t%l0\", ops);
        }
      output_asm_insn (\"dec\\t%h0\", operands);
      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
			         CODE_LABEL_NUMBER (ops[0]));
    }

  return \"\";
}")

;;
;; Split the special case where the source of the sign extend is
;; either Y or Z. In that case, we can't move the source in the D
;; register directly. The movhi pattern handles this move by using
;; a temporary scratch memory location.
;;
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
  "reload_completed && (Y_REG_P (operands[1]) || Z_REG_P (operands[1]))"
  [(set (reg:HI D_REGNUM) (match_dup 1))
   (set (match_dup 0) (sign_extend:SI (reg:HI D_REGNUM)))]
  "")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=D,D,D")
	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,!r,dA")))]
  ""
  "*
{
  rtx ops[2];
  int x_reg_used;

  if (Y_REG_P (operands[1]))
    return \"#\";

  if (X_REG_P (operands[1]))
    {
      output_asm_insn (\"xgdx\", operands);
      x_reg_used = 1;
    }
  else
    {
      /* X can be used as an indexed addressing in the source.
         Get the value before clearing it.  */
      x_reg_used = reg_mentioned_p (ix_reg, operands[1]);
      if (x_reg_used)
        {
	  ops[0] = gen_rtx (REG, HImode, HARD_D_REGNUM);
	  ops[1] = operands[1];
	  m68hc11_gen_movhi (insn, ops);
        }
    }

  CC_STATUS_INIT;
  if (TARGET_M6812 && 0)
    {
      /* This sequence of code is larger than the one for 68HC11.
         Don't use it; keep it for documentation.  */
      if (!D_REG_P (operands[1]) && !x_reg_used)
        {
          ops[0] = gen_rtx (REG, HImode, HARD_D_REGNUM);
          ops[1] = operands[1];
          m68hc11_gen_movhi (insn, ops);
        }
      output_asm_insn (\"sex\\ta,x\", operands);
      output_asm_insn (\"xgdx\", operands);
      output_asm_insn (\"sex\\ta,d\", operands);
      return \"xgdx\";
    }

  output_asm_insn (\"ldx\\t#0\", operands);
  if (D_REG_P (operands[1]) || x_reg_used)
    {
      output_asm_insn (\"tsta\", operands);
    }
  else
    {
      ops[0] = gen_rtx (REG, HImode, HARD_D_REGNUM);
      ops[1] = operands[1];
      m68hc11_gen_movhi (insn, ops);
    }

  ops[0] = gen_label_rtx ();
  output_asm_insn (\"bpl\\t%l0\", ops);
  output_asm_insn (\"dex\", operands);
  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[0]));

  return \"\";
}")


;;--------------------------------------------------------------------
;;- Min and Max instructions (68HC12).
;;--------------------------------------------------------------------
(define_insn "uminqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
	(umin:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
		 (match_operand:QI 2 "general_operand" "m,d")))]
  "TARGET_M6812 && TARGET_MIN_MAX"
  "*
{
  /* Flags are set according to (sub:QI (operand 1) (operand2)).
     The mina/minm use A as the source or destination.  This is the
     high part of D.  There is no way to express that in the pattern
     so we must use 'exg a,b' to put the operand in the good register.  */
  CC_STATUS_INIT;
  if (D_REG_P (operands[0]))
    {
      return \"exg\\ta,b\\n\\tmina\\t%2\\n\\texg\\ta,b\";
    }
  else
    {
      return \"exg\\ta,b\\n\\tminm\\t%0\\n\\texg\\ta,b\";
    }
}")

(define_insn "umaxqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
	(umax:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
		 (match_operand:QI 2 "general_operand" "m,d")))]
  "TARGET_M6812 && TARGET_MIN_MAX"
  "*
{
  /* Flags are set according to (sub:QI (operand 1) (operand2)).
     The maxa/maxm use A as the source or destination.  This is the
     high part of D.  There is no way to express that in the pattern
     so we must use 'exg a,b' to put the operand in the good register.  */
  CC_STATUS_INIT;
  if (D_REG_P (operands[0]))
    {
      return \"exg\\ta,b\\n\\tmaxa\\t%2\\n\\texg\\ta,b\";
    }
  else
    {
      return \"exg\\ta,b\\n\\tmaxm\\t%0\\n\\texg\\ta,b\";
    }
}")

(define_insn "uminhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
	(umin:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
		 (match_operand:HI 2 "general_operand" "m,d")))]
  "TARGET_M6812 && TARGET_MIN_MAX"
  "*
{
  /* Flags are set according to (sub:HI (operand 1) (operand2)).  */
  CC_STATUS_INIT;
  if (D_REG_P (operands[0]))
    {
      return \"emind\\t%2\";
    }
  else
    {
      return \"eminm\\t%0\";
    }
}")

(define_insn "umaxhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
	(umax:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
		 (match_operand:HI 2 "general_operand" "m,d")))]
  "TARGET_M6812 && TARGET_MIN_MAX"
  "*
{
  /* Flags are set according to (sub:HI (operand 1) (operand2)).  */
  CC_STATUS_INIT;
  if (D_REG_P (operands[0]))
    {
      return \"emaxd\\t%2\";
    }
  else
    {
      return \"emaxm\\t%0\";
    }
}")


;;--------------------------------------------------------------------
;;- Add instructions.
;;--------------------------------------------------------------------
;; 64-bit: Use a library call because what GCC generates is huge.
;;
(define_expand "adddi3"
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
	(plus:DI (match_operand:DI 1 "general_operand" "")
		 (match_operand:DI 2 "general_operand" "")))]
  ""
  "m68hc11_emit_libcall (\"___adddi3\", PLUS, DImode, DImode, 3, operands);
   DONE;")

;;
;; - 32-bit Add.
;;
(define_expand "addsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
	             (plus:SI (match_operand:SI 1 "general_operand" "")
		              (match_operand:SI 2 "general_operand" "")))