m68hc11.h

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   contents of class N.  The way the integer MASK is interpreted is
   that register R is in the class if `MASK & (1 << R)' is 1.  */

/*--------------------------------------------------------------
   X		0x00000001
   D		0x00000002
   Y		0x00000004
   SP		0x00000008
   PC		0x00000010
   A		0x00000020
   B		0x00000040
   CCR		0x00000080
   Z		0x00000100
   FRAME        0x00000200
   ZTMP		0x00000400
   ZREG		0x00000800
   XYREG	0x00001000
   FAKE         0x00002000
   Di		0xFFFFc000, 0x03FFF
   SFRAME       0x00000000, 0x04000
   AP           0x00000000, 0x08000

   D_OR_X_REGS represents D+X. It is used for 32-bits numbers.
   A_REGS      represents a valid base register for indexing. It represents
	       X,Y and the Z register.
   S_REGS      represents the soft-registers. This includes the hard frame
	       and soft frame registers.
--------------------------------------------------------------*/

#define REG_CLASS_CONTENTS \
/* NO_REGS */		{{ 0x00000000, 0x00000000 },			\
/* D_REGS  */		 { 0x00000002, 0x00000000 }, /* D */            \
/* X_REGS  */		 { 0x00000001, 0x00000000 }, /* X */            \
/* Y_REGS  */		 { 0x00000004, 0x00000000 }, /* Y */            \
/* SP_REGS */		 { 0x00000008, 0x00000000 }, /* SP */           \
/* DA_REGS */		 { 0x00000020, 0x00000000 }, /* A */            \
/* DB_REGS */		 { 0x00000040, 0x00000000 }, /* B */            \
/* Z_REGS  */		 { 0x00000100, 0x00000000 }, /* Z */            \
/* D8_REGS */		 { 0x00000060, 0x00000000 }, /* A B */          \
/* Q_REGS  */		 { 0x00000062, 0x00000000 }, /* A B D */        \
/* D_OR_X_REGS */        { 0x00000003, 0x00000000 }, /* D X */          \
/* D_OR_Y_REGS */        { 0x00000006, 0x00000000 }, /* D Y */          \
/* D_OR_SP_REGS */       { 0x0000000A, 0x00000000 }, /* D SP */         \
/* X_OR_Y_REGS  */	 { 0x00000005, 0x00000000 }, /* X Y */          \
/* A_REGS  */		 { 0x00000105, 0x00000000 }, /* X Y Z */        \
/* X_OR_SP_REGS */       { 0x00000009, 0x00000000 }, /* X SP */         \
/* Y_OR_SP_REGS */       { 0x0000000C, 0x00000000 }, /* Y SP */         \
/* X_OR_Y_OR_D_REGS */   { 0x00000007, 0x00000000 }, /* D X Y */        \
/* A_OR_D_REGS  */       { 0x00000107, 0x00000000 }, /* D X Y Z */      \
/* A_OR_SP_REGS */       { 0x0000010D, 0x00000000 }, /* X Y SP */       \
/* H_REGS  */		 { 0x0000010F, 0x00000000 }, /* D X Y SP */     \
/* S_REGS  */		 { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z*  */  \
/* D_OR_S_REGS */	 { 0xFFFFDE02, 0x00007FFF }, /* D _.D */        \
/* X_OR_S_REGS */	 { 0xFFFFDE01, 0x00007FFF }, /* X _.D */        \
/* Y_OR_S_REGS */	 { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */        \
/* Z_OR_S_REGS */	 { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */        \
/* SP_OR_S_REGS */	 { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */	\
/* D_OR_X_OR_S_REGS */	 { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */      \
/* D_OR_Y_OR_S_REGS */	 { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */      \
/* D_OR_SP_OR_S_REGS */	 { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */     \
/* A_OR_S_REGS */	 { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */      \
/* D_OR_A_OR_S_REGS */	 { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */    \
/* TMP_REGS  */	         { 0x00002000, 0x00000000 }, /* FAKE */		\
/* D_OR_A_OR_TMP_REGS*/  { 0x00002107, 0x00000000 }, /* D X Y Z Fake */  \
/* G_REGS  */		 { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */   \
/* ALL_REGS*/		 { 0xFFFFFFFF, 0x00007FFF }}


/* set up a C expression whose value is a register class containing hard
   register REGNO */
#define Q_REGNO_P(REGNO)	((REGNO) == HARD_A_REGNUM \
				 || (REGNO) == HARD_B_REGNUM)
#define Q_REG_P(X)              (REG_P (X) && Q_REGNO_P (REGNO (X)))

#define D_REGNO_P(REGNO)        ((REGNO) == HARD_D_REGNUM)
#define D_REG_P(X)              (REG_P (X) && D_REGNO_P (REGNO (X)))

#define DB_REGNO_P(REGNO)       ((REGNO) == HARD_B_REGNUM)
#define DB_REG_P(X)             (REG_P (X) && DB_REGNO_P (REGNO (X)))
#define DA_REGNO_P(REGNO)       ((REGNO) == HARD_A_REGNUM)
#define DA_REG_P(X)             (REG_P (X) && DA_REGNO_P (REGNO (X)))

#define X_REGNO_P(REGNO)        ((REGNO) == HARD_X_REGNUM)
#define X_REG_P(X)              (REG_P (X) && X_REGNO_P (REGNO (X)))

#define Y_REGNO_P(REGNO)        ((REGNO) == HARD_Y_REGNUM)
#define Y_REG_P(X)              (REG_P (X) && Y_REGNO_P (REGNO (X)))

#define Z_REGNO_P(REGNO)        ((REGNO) == HARD_Z_REGNUM)
#define Z_REG_P(X)              (REG_P (X) && Z_REGNO_P (REGNO (X)))

#define SP_REGNO_P(REGNO)       ((REGNO) == HARD_SP_REGNUM)
#define SP_REG_P(X)             (REG_P (X) && SP_REGNO_P (REGNO (X)))

/* Address register.  */
#define A_REGNO_P(REGNO)        ((REGNO) == HARD_X_REGNUM \
                                 || (REGNO) == HARD_Y_REGNUM \
                                 || (REGNO) == HARD_Z_REGNUM)
#define A_REG_P(X)              (REG_P (X) && A_REGNO_P (REGNO (X)))

/* M68hc11 hard registers.  */
#define H_REGNO_P(REGNO)        (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \
				 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO))
#define H_REG_P(X)              (REG_P (X) && H_REGNO_P (REGNO (X)))

#define FAKE_REGNO_P(REGNO)     ((REGNO) == FAKE_CLOBBER_REGNUM)
#define FAKE_REG_P(X)           (REG_P (X) && FAKE_REGNO_P (REGNO (X)))

/* Soft registers (or register emulation for gcc).  The temporary register
   used by insn template must be part of the S_REGS class so that it
   matches the 'u' constraint.  */
#define S_REGNO_P(REGNO)        ((REGNO) >= SOFT_TMP_REGNUM \
                                 && (REGNO) <= SOFT_REG_LAST \
                                 && (REGNO) != FAKE_CLOBBER_REGNUM)
#define S_REG_P(X)              (REG_P (X) && S_REGNO_P (REGNO (X)))

#define Z_REGNO_P(REGNO)        ((REGNO) == HARD_Z_REGNUM)
#define Z_REG_P(X)              (REG_P (X) && Z_REGNO_P (REGNO (X)))

/* General register.  */
#define G_REGNO_P(REGNO)        (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \
                                 || ((REGNO) == HARD_PC_REGNUM) \
				 || ((REGNO) == HARD_FP_REGNUM) \
				 || ((REGNO) == SOFT_FP_REGNUM) \
				 || ((REGNO) == FAKE_CLOBBER_REGNUM) \
				 || ((REGNO) == SOFT_AP_REGNUM))

#define G_REG_P(X)              (REG_P (X) && G_REGNO_P (REGNO (X)))

#define REGNO_REG_CLASS(REGNO) \
  (D_REGNO_P (REGNO) ? D_REGS : \
   (X_REGNO_P (REGNO) ? X_REGS : \
    (Y_REGNO_P (REGNO) ? Y_REGS : \
     (SP_REGNO_P (REGNO) ? SP_REGS : \
      (Z_REGNO_P (REGNO) ? Z_REGS : \
       (H_REGNO_P (REGNO) ? H_REGS : \
        (FAKE_REGNO_P (REGNO) ? TMP_REGS : \
	 (S_REGNO_P (REGNO) ? S_REGS : \
	  (DA_REGNO_P (REGNO) ? DA_REGS: \
	   (DB_REGNO_P (REGNO) ? DB_REGS: \
            (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS)))))))))))


/* Get reg_class from a letter in the machine description.  */

extern enum reg_class m68hc11_tmp_regs_class;
#define REG_CLASS_FROM_LETTER(C) \
   ((C) == 'a' ? DA_REGS : \
    (C) == 'A' ? A_REGS : \
    (C) == 'b' ? DB_REGS : \
    (C) == 'B' ? X_OR_Y_REGS : \
    (C) == 'd' ? D_REGS : \
    (C) == 'D' ? D_OR_X_REGS : \
    (C) == 'q' ? Q_REGS : \
    (C) == 'h' ? H_REGS : \
    (C) == 't' ? TMP_REGS : \
    (C) == 'u' ? S_REGS : \
    (C) == 'v' ? m68hc11_tmp_regs_class : \
    (C) == 'w' ? SP_REGS : \
    (C) == 'x' ? X_REGS : \
    (C) == 'y' ? Y_REGS : \
    (C) == 'z' ? Z_REGS : NO_REGS)

#define PREFERRED_RELOAD_CLASS(X,CLASS)	preferred_reload_class(X,CLASS)

#define SMALL_REGISTER_CLASSES 1

/* A C expression that is nonzero if hard register number REGNO2 can be
   considered for use as a rename register for REGNO1 */

#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
  m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2))

/* A C expression whose value is nonzero if pseudos that have been
   assigned to registers of class CLASS would likely be spilled
   because registers of CLASS are needed for spill registers.

   The default value of this macro returns 1 if CLASS has exactly one
   register and zero otherwise.  On most machines, this default
   should be used.  Only define this macro to some other expression
   if pseudo allocated by `local-alloc.c' end up in memory because
   their hard registers were needed for spill registers.  If this
   macro returns nonzero for those classes, those pseudos will only
   be allocated by `global.c', which knows how to reallocate the
   pseudo to another register.  If there would not be another
   register available for reallocation, you should not change the
   definition of this macro since the only effect of such a
   definition would be to slow down register allocation.  */

#define CLASS_LIKELY_SPILLED_P(CLASS)					\
  (((CLASS) == D_REGS)							\
   || ((CLASS) == X_REGS)                                               \
   || ((CLASS) == Y_REGS)                                               \
   || ((CLASS) == A_REGS)                                               \
   || ((CLASS) == SP_REGS)                                              \
   || ((CLASS) == D_OR_X_REGS)                                          \
   || ((CLASS) == D_OR_Y_REGS)                                          \
   || ((CLASS) == X_OR_SP_REGS)                                         \
   || ((CLASS) == Y_OR_SP_REGS)                                         \
   || ((CLASS) == D_OR_SP_REGS))

/* Return the maximum number of consecutive registers needed to represent
   mode MODE in a register of class CLASS.  */
#define CLASS_MAX_NREGS(CLASS, MODE)		\
(((CLASS) == DA_REGS || (CLASS) == DB_REGS \
   || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \
 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

/* The letters I, J, K, L and M in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.

   `K' is for 0.
   `L' is for range -65536 to 65536
   `M' is for values whose 16-bit low part is 0
   'N' is for +1 or -1.
   'O' is for 16 (for rotate using swap).
   'P' is for range -8 to 2 (used by addhi_sp)

   'I', 'J' are not used.  */

#define CONST_OK_FOR_LETTER_P(VALUE, C) \
  ((C) == 'K' ? (VALUE) == 0 : \
   (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \
   (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \
   (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \
   (C) == 'I' ? ((VALUE) >= -2 && (VALUE) <= 2) : \
   (C) == 'O' ? (VALUE) == 16 : \
   (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0)

/* Similar, but for floating constants, and defining letters G and H.

   `G' is for 0.0.  */
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
		 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0) 

/* 'U' represents certain kind of memory indexed operand for 68HC12.
   and any memory operand for 68HC11.  */
#define EXTRA_CONSTRAINT(OP, C)                         \
((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \
 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \
 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \
 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \
		 && non_push_operand (OP, GET_MODE (OP))) : 0)


/* Stack layout; function entry, exit and calling.  */

/* Define this if pushing a word on the stack
   makes the stack pointer a smaller address.  */
#define STACK_GROWS_DOWNWARD

/* Define this if the nominal address of the stack frame
   is at the high-address end of the local variables;
   that is, each additional local variable allocated
   goes at a more negative offset in the frame.

   Don't define for 68HC11, the frame pointer is the bottom
   of local variables.  */
/* #define FRAME_GROWS_DOWNWARD */

/* Define this if successive arguments to a function occupy decreasing 
   addresses in the stack.  */
/* #define ARGS_GROW_DOWNWARD */

/* Offset within stack frame to start allocating local variables at.
   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
   first local allocated.  Otherwise, it is the offset to the BEGINNING
   of the first local allocated.  */
#define STARTING_FRAME_OFFSET		0

/* Offset of first parameter from the argument pointer register value.  */

#define FIRST_PARM_OFFSET(FNDECL)	2

/* After the prologue, RA is at 0(AP) in the current frame.  */
#define RETURN_ADDR_RTX(COUNT, FRAME)					\
  ((COUNT) == 0								\
   ? gen_rtx_MEM (Pmode, arg_pointer_rtx)                               \
   : 0)

/* Before the prologue, the top of the frame is at 2(sp).  */
#define INCOMING_FRAME_SP_OFFSET        2

/* Define this if functions should assume that stack space has been
   allocated for arguments even when their values are passed in
   registers.
  
   The value of this macro is the size, in bytes, of the area reserved for
   arguments passed in registers.
  
   This space can either be allocated by the caller or be a part of the
   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
   says which.  */
/* #define REG_PARM_STACK_SPACE(FNDECL)	2 */

/* Define this macro if REG_PARM_STACK_SPACE is defined but stack
   parameters don't skip the area specified by REG_PARM_STACK_SPACE.
   Normally, when a parameter is not passed in registers, it is placed on
   the stack beyond the REG_PARM_STACK_SPACE area.  Defining this macro  
   suppresses this behavior and causes the parameter to be passed on the
   stack in its natural location.  */
/* #define STACK_PARMS_IN_REG_PARM_AREA */

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM		HARD_SP_REGNUM

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM		SOFT_FP_REGNUM

#define HARD_FRAME_POINTER_REGNUM	HARD_FP_REGNUM

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM		SOFT_AP_REGNUM