rs6000.h

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/* Define this macro to be the value 1 if unaligned accesses have a cost
   many times greater than aligned accesses, for example if they are
   emulated in a trap handler.  */
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN)				\
  (STRICT_ALIGNMENT							\
   || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode	\
	|| (MODE) == DImode)						\
       && (ALIGN) < 32))

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.

   RS/6000 has 32 fixed-point registers, 32 floating-point registers,
   an MQ register, a count register, a link register, and 8 condition
   register fields, which we view here as separate registers.

   In addition, the difference between the frame and argument pointers is
   a function of the number of registers saved, so we need to have a
   register for AP that will later be eliminated in favor of SP or FP.
   This is a normal register, but it is fixed.

   We also create a pseudo register for float/int conversions, that will
   really represent the memory location used.  It is represented here as
   a register, in order to work around problems in allocating stack storage
   in inline functions.  */

#define FIRST_PSEUDO_REGISTER 113

/* This must be included for pre gcc 3.0 glibc compatibility.  */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.

   On RS/6000, r1 is used for the stack.  On Darwin, r2 is available
   as a local register; for all other OS's r2 is the TOC pointer.

   cr5 is not supposed to be used.

   On System V implementations, r13 is fixed and not available for use.  */

#define FIXED_REGISTERS  \
  {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1,	   \
   /* AltiVec registers.  */			   \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1						   \
   , 1, 1                                          \
}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */

#define CALL_USED_REGISTERS  \
  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1,	   \
   /* AltiVec registers.  */			   \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1						   \
   , 1, 1                                          \
}

/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
   the entire set of `FIXED_REGISTERS' be included.
   (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
   This macro is optional.  If not specified, it defaults to the value
   of `CALL_USED_REGISTERS'.  */
		       
#define CALL_REALLY_USED_REGISTERS  \
  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1,	   \
   /* AltiVec registers.  */			   \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0						   \
   , 0, 0                                          \
}

#define MQ_REGNO     64
#define CR0_REGNO    68
#define CR1_REGNO    69
#define CR2_REGNO    70
#define CR3_REGNO    71
#define CR4_REGNO    72
#define MAX_CR_REGNO 75
#define XER_REGNO    76
#define FIRST_ALTIVEC_REGNO	77
#define LAST_ALTIVEC_REGNO	108
#define TOTAL_ALTIVEC_REGS	(LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
#define VRSAVE_REGNO		109
#define VSCR_REGNO		110
#define SPE_ACC_REGNO		111
#define SPEFSCR_REGNO		112

/* List the order in which to allocate registers.  Each register must be
   listed once, even those in FIXED_REGISTERS.

   We allocate in the following order:
	fp0		(not saved or used for anything)
	fp13 - fp2	(not saved; incoming fp arg registers)
	fp1		(not saved; return value)
 	fp31 - fp14	(saved; order given to save least number)
	cr7, cr6	(not saved or special)
	cr1		(not saved, but used for FP operations)
	cr0		(not saved, but used for arithmetic operations)
	cr4, cr3, cr2	(saved)
        r0		(not saved; cannot be base reg)
	r9		(not saved; best for TImode)
	r11, r10, r8-r4	(not saved; highest used first to make less conflict)
	r3     		(not saved; return value register)
	r31 - r13	(saved; order given to save least number)
	r12		(not saved; if used for DImode or DFmode would use r13)
	mq		(not saved; best to use it if we can)
	ctr		(not saved; when we have the choice ctr is better)
	lr		(saved)
        cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
	spe_acc, spefscr (fixed)

	AltiVec registers:
	v0 - v1         (not saved or used for anything)
	v13 - v3        (not saved; incoming vector arg registers)
	v2              (not saved; incoming vector arg reg; return value)
	v19 - v14       (not saved or used for anything)
	v31 - v20       (saved; order given to save least number)
*/
						

#define REG_ALLOC_ORDER					\
  {32, 							\
   45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34,	\
   33,							\
   63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51,	\
   50, 49, 48, 47, 46, 					\
   75, 74, 69, 68, 72, 71, 70,				\
   0,							\
   9, 11, 10, 8, 7, 6, 5, 4,				\
   3,							\
   31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,	\
   18, 17, 16, 15, 14, 13, 12,				\
   64, 66, 65, 						\
   73, 1, 2, 67, 76,					\
   /* AltiVec registers.  */				\
   77, 78,						\
   90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80,		\
   79,							\
   96, 95, 94, 93, 92, 91,				\
   108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98,	\
   97, 109, 110						\
   , 111, 112                                              \
}

/* True if register is floating-point.  */
#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)

/* True if register is a condition register.  */
#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)

/* True if register is a condition register, but not cr0.  */
#define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)

/* True if register is an integer register.  */
#define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)

/* SPE SIMD registers are just the GPRs.  */
#define SPE_SIMD_REGNO_P(N) ((N) <= 31)

/* True if register is the XER register.  */
#define XER_REGNO_P(N) ((N) == XER_REGNO)

/* True if register is an AltiVec register.  */
#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   For the SPE, GPRs are 64 bits but only 32 bits are visible in
   scalar instructions.  The upper 32 bits are only available to the
   SIMD instructions.

   POWER and PowerPC GPRs hold 32 bits worth;
   PowerPC64 GPRs and FPRs point register holds 64 bits worth.  */

#define HARD_REGNO_NREGS(REGNO, MODE)					\
  (FP_REGNO_P (REGNO)							\
   ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
   : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE))   \
   ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
   : ALTIVEC_REGNO_P (REGNO)						\
   ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

#define ALTIVEC_VECTOR_MODE(MODE)	\
	 ((MODE) == V16QImode		\
	  || (MODE) == V8HImode		\
	  || (MODE) == V4SFmode		\
	  || (MODE) == V4SImode)

#define SPE_VECTOR_MODE(MODE)		\
	((MODE) == V4HImode          	\
         || (MODE) == V2SFmode          \
         || (MODE) == V1DImode          \
         || (MODE) == V2SImode)

/* Define this macro to be nonzero if the port is prepared to handle
   insns involving vector mode MODE.  At the very least, it must have
   move patterns for this mode.  */

#define VECTOR_MODE_SUPPORTED_P(MODE)			\
        ((TARGET_SPE && SPE_VECTOR_MODE (MODE))		\
	 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   For POWER and PowerPC, the GPRs can hold any mode, but the float
   registers only can hold floating modes and DImode, and CR register only
   can hold CC modes.  We cannot put TImode anywhere except general
   register and it must be able to fit within the register set.  */

#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
  (FP_REGNO_P (REGNO) ?							\
   (GET_MODE_CLASS (MODE) == MODE_FLOAT					\
    || (GET_MODE_CLASS (MODE) == MODE_INT				\
	&& GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD))			\
   : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE)		\
   : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
   : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC		\
   : XER_REGNO_P (REGNO) ? (MODE) == PSImode				\
   : ! INT_REGNO_P (REGNO) ? GET_MODE_SIZE (MODE) <= UNITS_PER_WORD	\
   : 1)

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2) \
  (GET_MODE_CLASS (MODE1) == MODE_FLOAT		\
   ? GET_MODE_CLASS (MODE2) == MODE_FLOAT	\
   : GET_MODE_CLASS (MODE2) == MODE_FLOAT	\
   ? GET_MODE_CLASS (MODE1) == MODE_FLOAT	\
   : GET_MODE_CLASS (MODE1) == MODE_CC		\
   ? GET_MODE_CLASS (MODE2) == MODE_CC		\
   : GET_MODE_CLASS (MODE2) == MODE_CC		\
   ? GET_MODE_CLASS (MODE1) == MODE_CC		\
   : ALTIVEC_VECTOR_MODE (MODE1)		\
   ? ALTIVEC_VECTOR_MODE (MODE2)		\
   : ALTIVEC_VECTOR_MODE (MODE2)		\
   ? ALTIVEC_VECTOR_MODE (MODE1)		\
   : 1)

/* A C expression returning the cost of moving data from a register of class
   CLASS1 to one of CLASS2.  */

#define REGISTER_MOVE_COST rs6000_register_move_cost

/* A C expressions returning the cost of moving data of MODE from a register to
   or from memory.  */

#define MEMORY_MOVE_COST rs6000_memory_move_cost

/* Specify the cost of a branch insn; roughly the number of extra insns that
   should be added to avoid a branch.

   Set this to 3 on the RS/6000 since that is roughly the average cost of an
   unscheduled conditional branch.  */

#define BRANCH_COST 3


/* A fixed register used at prologue and epilogue generation to fix
   addressing modes.  The SPE needs heavy addressing fixes at the last
   minute, and it's best to save a register for it.

   AltiVec also needs fixes, but we've gotten around using r11, which
   is actually wrong because when use_backchain_to_restore_sp is true,
   we end up clobbering r11.

   The AltiVec case needs to be fixed.  Dunno if we should break ABI
   compatability and reserve a register for it as well..  */

#define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)

/* Define this macro to change register usage conditional on target flags.
   Set MQ register fixed (already call_used) if not POWER architecture
   (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
   64-bit AIX reserves GPR13 for thread-private data.
   Conditionally disable FPRs.  */

#define CONDITIONAL_REGISTER_USAGE					\
{									\
  int i;								\
  if (! TARGET_POWER)							\
    fixed_regs[64] = 1;							\
  if (TARGET_64BIT)							\
    fixed_regs[13] = call_used_regs[13]					\
      = call_really_used_regs[13] = 1; 					\
  if (TARGET_SOFT_FLOAT || !TARGET_FPRS)				\
    for (i = 32; i < 64; i++)						\
      fixed_regs[i] = call_used_regs[i]					\
        = call_really_used_regs[i] = 1;					\
  if (DEFAULT_ABI == ABI_V4						\
      && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM			\
      && flag_pic == 2)							\
    fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;			\
  if (DEFAULT_ABI == ABI_V4						\
      && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM			\
      && flag_pic == 1)							\
    fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]				\
      = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]			\
      = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;	\
  if (DEFAULT_ABI == ABI_DARWIN						\
      && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)			\
    global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]				\
      = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]			\
      = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]			\
      = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;	\
  if (TARGET_ALTIVEC)                                                   \
    global_regs[VSCR_REGNO] = 1;                                        \
  if (TARGET_SPE)							\
    {                                                                   \