rs6000.md

linux下的gcc编译器

   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 2 ""))]
  "! TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 2)
	(not:SI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")

(define_insn ""
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(not:SI (match_dup 1)))]
  "! TARGET_POWERPC64"
  "@
   nor. %0,%1,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(not:SI (match_dup 1)))]
  "! TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 0)
	(not:SI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
		  (match_operand:SI 2 "gpc_reg_operand" "r")))]
  "! TARGET_POWERPC"
  "{sf%I1|subf%I1c} %0,%2,%1")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
		  (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
  "TARGET_POWERPC"
  "@
   subf %0,%2,%1
   subfic %0,%2,%1")

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (clobber (match_scratch:SI 3 "=r,r"))]
  "! TARGET_POWERPC"
  "@
   {sf.|subfc.} %3,%2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (clobber (match_scratch:SI 3 "=r,r"))]
  "TARGET_POWERPC && ! TARGET_POWERPC64"
  "@
   subf. %3,%2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_operand:SI 2 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 3 ""))]
  "! TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 3)
	(minus:SI (match_dup 1)
		  (match_dup 2)))
   (set (match_dup 0)
	(compare:CC (match_dup 3)
		    (const_int 0)))]
  "")

(define_insn ""
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(minus:SI (match_dup 1) (match_dup 2)))]
  "! TARGET_POWERPC"
  "@
   {sf.|subfc.} %0,%2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_insn ""
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(minus:SI (match_dup 1)
		  (match_dup 2)))]
  "TARGET_POWERPC && ! TARGET_POWERPC64"
  "@
   subf. %0,%2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_operand:SI 2 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(minus:SI (match_dup 1)
		  (match_dup 2)))]
  "! TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 0)
	(minus:SI (match_dup 1)
		  (match_dup 2)))
   (set (match_dup 3)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")

(define_expand "subsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
		  (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      emit_insn (gen_addsi3 (operands[0], operands[1],
			     negate_rtx (SImode, operands[2])));
      DONE;
    }
}")

;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
;; instruction and some auxiliary computations.  Then we just have a single
;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
;; combine.

(define_expand "sminsi3"
  [(set (match_dup 3)
	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
				(match_operand:SI 2 "reg_or_short_operand" ""))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(minus:SI (match_dup 2) (match_dup 3)))]
  "TARGET_POWER || TARGET_ISEL"
  "
{
  if (TARGET_ISEL)
    {
      operands[2] = force_reg (SImode, operands[2]);
      rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
      DONE;
    }

  operands[3] = gen_reg_rtx (SImode);
}")

(define_split
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
		 (match_operand:SI 2 "reg_or_short_operand" "")))
   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
  "TARGET_POWER"
  [(set (match_dup 3)
	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
  "")

(define_expand "smaxsi3"
  [(set (match_dup 3)
	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
				(match_operand:SI 2 "reg_or_short_operand" ""))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(plus:SI (match_dup 3) (match_dup 1)))]
  "TARGET_POWER || TARGET_ISEL"
  "
{
  if (TARGET_ISEL)
    {
      operands[2] = force_reg (SImode, operands[2]);
      rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
      DONE;
    }
  operands[3] = gen_reg_rtx (SImode);
}")

(define_split
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
		 (match_operand:SI 2 "reg_or_short_operand" "")))
   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
  "TARGET_POWER"
  [(set (match_dup 3)
	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
  "")

(define_expand "uminsi3"
  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_dup 5)))
   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
			      (match_dup 5)))
   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
				       (const_int 0)
				       (minus:SI (match_dup 4) (match_dup 3))))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(minus:SI (match_dup 2) (match_dup 3)))]
  "TARGET_POWER || TARGET_ISEL"
  "
{
  if (TARGET_ISEL)
    {
      rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
      DONE;
    }
  operands[3] = gen_reg_rtx (SImode);
  operands[4] = gen_reg_rtx (SImode);
  operands[5] = GEN_INT (-2147483647 - 1);
}")

(define_expand "umaxsi3"
  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_dup 5)))
   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
			      (match_dup 5)))
   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
				       (const_int 0)
				       (minus:SI (match_dup 4) (match_dup 3))))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(plus:SI (match_dup 3) (match_dup 1)))]
  "TARGET_POWER || TARGET_ISEL"
  "
{
  if (TARGET_ISEL)
    {
      rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
      DONE;
    }
  operands[3] = gen_reg_rtx (SImode);
  operands[4] = gen_reg_rtx (SImode);
  operands[5] = GEN_INT (-2147483647 - 1);
}")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))]
  "TARGET_POWER"
  "doz%I2 %0,%1,%2")

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (clobber (match_scratch:SI 3 "=r,r"))]
  "TARGET_POWER"
  "@
   doz%I2. %3,%1,%2
   #"
  [(set_attr "type" "delayed_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_operand:SI 2 "reg_or_short_operand" ""))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (clobber (match_scratch:SI 3 ""))]
  "TARGET_POWER && reload_completed"
  [(set (match_dup 3)
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_dup 0)
	(compare:CC (match_dup 3)
		    (const_int 0)))]
  "")

(define_insn ""
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))]
  "TARGET_POWER"
  "@
   doz%I2. %0,%1,%2
   #"
  [(set_attr "type" "delayed_compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
	(compare:CC
	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
			      (match_operand:SI 2 "reg_or_short_operand" ""))
			  (const_int 0)
			  (minus:SI (match_dup 2) (match_dup 1)))
	 (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))]
  "TARGET_POWER && reload_completed"
  [(set (match_dup 0)
	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
			 (const_int 0)
			 (minus:SI (match_dup 2) (match_dup 1))))
   (set (match_dup 3)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")

;; We don't need abs with condition code because such comparisons should
;; never be done.
(define_expand "abssi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
  ""
  "
{
  if (TARGET_ISEL)
    {
      emit_insn (gen_abssi2_isel (operands[0], operands[1]));
      DONE;
    }
  else if (! TARGET_POWER)
    {
      emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
      DONE;
    }
}")

(define_insn "*abssi2_power"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
  "TARGET_POWER"
  "abs %0,%1")

(define_insn_and_split "abssi2_isel"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
   (clobber (match_scratch:SI 2 "=b"))
   (clobber (match_scratch:CC 3 "=y"))]
  "TARGET_ISEL"
  "#"
  "&& reload_completed"
  [(set (match_dup 2) (neg:SI (match_dup 1)))
   (set (match_dup 3)
	(compare:CC (match_dup 1)
		    (const_int 0)))
   (set (match_dup 0)
	(if_then_else:SI (ge (match_dup 3)
			     (const_int 0))
			 (match_dup 1)
			 (match_dup 2)))]
  "")

(define_insn_and_split "abssi2_nopower"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
   (clobber (match_scratch:SI 2 "=&r,&r"))]
  "! TARGET_POWER && ! TARGET_ISEL"
  "#"
  "&& reload_completed"
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
  "")

(define_insn "*nabs_power"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
  "TARGET_POWER"
  "nabs %0,%1")

(define_insn_and_split "*nabs_nopower"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
        (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
   (clobber (match_scratch:SI 2 "=&r,&r"))]
  "! TARGET_POWER"
  "#"
  "&& reload_completed"
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
  "")

(define_insn "negsi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
  ""
  "neg %0,%1")

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (clobber (match_scratch:SI 2 "=r,r"))]
  "! TARGET_POWERPC64"
  "@
   neg. %2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 2 ""))]
  "! TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 2)
	(neg:SI (