rs6000.md

linux下的gcc编译器

       (eq_attr "cpu" "ppc750,ppc7400"))
  3 2)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul3")
       (eq_attr "cpu" "ppc750,ppc7400"))
  2 1)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc750,ppc7400"))
  19 19)

; CR-logical operations are execute-serialized, that is they don't
; start (and block the function unit) until all preceding operations
; have finished.  They don't block dispatch of other insns, though.
; I've imitated this by giving them longer latency.
(define_function_unit "sru" 1 0 
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "ppc603,ppc750,ppc7400"))
  3 2)

; compare is done on integer unit, but feeds insns which
; execute on the branch unit.
(define_function_unit "iu" 1 0   
  (and (eq_attr "type" "compare")
       (eq_attr "cpu" "rios1"))
  4 1)

(define_function_unit "iu" 1 0   
  (and (eq_attr "type" "delayed_compare")
       (eq_attr "cpu" "rios1"))
  5 1)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "compare,delayed_compare")
       (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603"))
  3 1)

; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare
; and a following branch, to reduce mispredicts
(define_function_unit "iu3" 3 0
  (and (eq_attr "type" "compare,delayed_compare")
       (eq_attr "cpu" "ppc7450"))
  1 1)

(define_function_unit "iu2" 2 0   
  (and (eq_attr "type" "compare,delayed_compare")
       (eq_attr "cpu" "rios2"))
  3 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "compare,delayed_compare")
       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
  1 1)

; fp compare uses fp unit
(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "rios1"))
  9 1)

; rios1 and rios2 have different fpcompare delays
(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "rios2,ppc630"))
  5 1)

; on ppc601 and ppc603, fpcompare takes also 2 cycles from
; the integer unit
; here we do not define delays, just occupy the unit. The dependencies
; will be assigned by the fpcompare definition in the fpu.
(define_function_unit "iu" 1 0
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "ppc601,ppc603"))
  0 2)

; fp compare uses fp unit
(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620"))
  5 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu"  "ppc750,ppc7400,ppc7450"))
  3 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "mpccore"))
  1 1)

(define_function_unit "bpu" 1 0
  (and (eq_attr "type" "mtjmpr")
       (eq_attr "cpu" "rios1,rios2,rs64a"))
  5 1)

(define_function_unit "bpu" 1 0
  (and (eq_attr "type" "mtjmpr")
       (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
  4 1)

(define_function_unit "sru" 1 0
  (and (eq_attr "type" "mtjmpr")
       (eq_attr "cpu" "ppc750,ppc7400"))
  2 2)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "mtjmpr")
       (eq_attr "cpu" "ppc7450"))
  2 2)

(define_function_unit "bpu" 1 0
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "rios1,rios2,ppc604"))
  4 1)
  
(define_function_unit "cru" 1 0
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a"))
  1 1)

; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
(define_function_unit "bpu" 1 0
  (eq_attr "type" "jmpreg")
  1 1)

(define_function_unit "bpu" 1 0
  (eq_attr "type" "branch")
  1 1)

; Floating Point Unit
(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fp,dmul")
       (eq_attr "cpu" "rios1"))
  2 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fp")
       (eq_attr "cpu" "rs64a,mpccore"))
  4 2)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fp")
       (eq_attr "cpu" "ppc601"))
  4 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fp")
       (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400"))
  3 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fp,dmul")
       (eq_attr "cpu" "ppc7450"))
  5 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "dmul")
       (eq_attr "cpu" "rs64a"))
  7 2)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "dmul")
       (eq_attr "cpu" "mpccore"))
  5 5)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "dmul")
       (eq_attr "cpu" "ppc601"))
  5 2)

; is this true?
(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "dmul")
       (eq_attr "cpu" "ppc603,ppc750"))
  4 2)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "dmul")
       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400"))
  3 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "sdiv,ddiv")
       (eq_attr "cpu" "rios1"))
  19 19)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "rs64a"))
  31 31)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "ppc601,ppc750,ppc7400"))
  17 17)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "ppc7450"))
  21 21)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "mpccore"))
  10 10)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
  18 18)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "mpccore"))
  17 17)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400"))
  31 31)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "ppc7450"))
  35 35)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "ppc603"))
  33 33)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "ssqrt")
       (eq_attr "cpu" "ppc620"))
  31 31)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "dsqrt")
       (eq_attr "cpu" "ppc620"))
  31 31)

; RIOS2 has two symmetric FPUs.
(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "fp,dmul")
       (eq_attr "cpu" "rios2"))
  2 1)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "fp,dmul")
       (eq_attr "cpu" "ppc630"))
  3 1)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "sdiv,ddiv")
       (eq_attr "cpu" "rios2"))
  17 17)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "ppc630"))
  17 17)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "ppc630"))
  21 21)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "ssqrt,dsqrt")
       (eq_attr "cpu" "rios2"))
  26 26)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "ssqrt")
       (eq_attr "cpu" "ppc630"))
  18 18)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "dsqrt")
       (eq_attr "cpu" "ppc630"))
  26 26)

;; Power4
(define_function_unit "lsu2" 2 0
  (and (eq_attr "type" "load")
       (eq_attr "cpu" "power4"))
  3 1)

(define_function_unit "lsu2" 2 0
  (and (eq_attr "type" "fpload")
       (eq_attr "cpu" "power4"))
  5 1)

(define_function_unit "lsu2" 2 0
  (and (eq_attr "type" "store,fpstore")
       (eq_attr "cpu" "power4"))
  1 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "integer")
       (eq_attr "cpu" "power4"))
  2 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "lmul")
       (eq_attr "cpu" "power4"))
  7 6)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "power4"))
  5 4)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "imul2,imul3")
       (eq_attr "cpu" "power4"))
  4 3)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "power4"))
  36 35)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "ldiv")
       (eq_attr "cpu" "power4"))
  68 67)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "power4"))
  36 35)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "ldiv")
       (eq_attr "cpu" "power4"))
  68 67)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "compare")
       (eq_attr "cpu" "power4"))
  3 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "delayed_compare")
       (eq_attr "cpu" "power4"))
  4 1)

(define_function_unit "bpu" 1 0
  (and (eq_attr "type" "mtjmpr")
       (eq_attr "cpu" "power4"))
  3 1)

(define_function_unit "bpu" 1 0
  (and (eq_attr "type" "jmpreg,branch")
       (eq_attr "cpu" "power4"))
  2 1)

(define_function_unit "cru" 1 0
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "power4"))
  4 1)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "fp,dmul")
       (eq_attr "cpu" "power4"))
  6 1)

; adjust_cost increases the cost of dependent branches,
; so shave a few cycles off for fpcompare.
(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "power4"))
  5 1)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "sdiv,ddiv")
       (eq_attr "cpu" "power4"))
  33 28)

(define_function_unit "fpu2" 2 0
  (and (eq_attr "type" "ssqrt,dsqrt")
       (eq_attr "cpu" "power4"))
  40 35)


;; Start with fixed-point load and store insns.  Here we put only the more
;; complex forms.  Basic data transfer is done later.

(define_expand "zero_extendqidi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
	(zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
  "TARGET_POWERPC64"
  "")

(define_insn ""
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
	(zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
  "TARGET_POWERPC64"
  "@
   lbz%U1%X1 %0,%1
   rldicl %0,%1,0,56"
  [(set_attr "type" "load,*")])

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (clobber (match_scratch:DI 2 "=r,r"))]
  "TARGET_POWERPC64"
  "@
   rldicl. %2,%1,0,56
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:DI 2 ""))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 2)
	(zero_extend:DI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")

(define_insn ""
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
		    (const_int 0)))
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
	(zero_extend:DI (match_dup 1)))]
  "TARGET_POWERPC64"
  "@
   rldicl. %0,%1,0,56
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:DI 0 "gpc_reg_operand" "")
	(zero_extend:DI (match_dup 1)))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 0)
	(zero_extend:DI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")

(define_insn "extendqidi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
  "TARGET_POWERPC64"
  "extsb %0,%1")

(define_insn ""
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")