rs6000.md

linux下的gcc编译器

;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 
;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
;; Contributed by Richard Kenner ([e-mail])

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;; `unspec' values used in rs6000.md:
;; Number	Use
;; 0		frsp for POWER machines
;; 0/v		blockage
;; 5		used to tie the stack contents and the stack pointer
;; 6		address of a word pointing to the TOC
;; 7		address of the TOC (more-or-less)
;; 8		movsi_got
;; 9/v		eh_reg_restore
;; 10		fctiwz
;; 15		load_macho_picbase
;; 16		macho_correct_pic
;; 19		movesi_from_cr
;; 20		movesi_to_cr

;; Define an insn type attribute.  This is used in function unit delay
;; computations.
(define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec"
  (const_string "integer"))

;; Length (in bytes).
; '(pc)' in the following doesn't include the instruction itself; it is 
; calculated as if the instruction had zero size.
(define_attr "length" ""
  (if_then_else (eq_attr "type" "branch")
		(if_then_else (and (ge (minus (match_dup 0) (pc))
				       (const_int -32768))
				   (lt (minus (match_dup 0) (pc))
				       (const_int 32764)))
			      (const_int 4)
			      (const_int 8))
		(const_int 4)))

;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.

(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
  (const (symbol_ref "rs6000_cpu_attr")))

; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
;			TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])

; Load/Store Unit -- pure PowerPC only
; (POWER and 601 use Integer Unit)
(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "load")
       (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
  2 1)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "load,vecload")
       (eq_attr "cpu" "ppc7450"))
  3 1)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "store,fpstore")
       (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630"))
  1 1)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "store,fpstore")
       (eq_attr "cpu" "ppc750,ppc7400"))
  2 1)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "store,vecstore")
       (eq_attr "cpu" "ppc7450"))
  3 1)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "fpstore")
       (eq_attr "cpu" "ppc7450"))
  3 3)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "fpload")
       (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400"))
  2 1)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "fpload")
       (eq_attr "cpu" "ppc7450"))
  4 1)

(define_function_unit "lsu" 1 0
  (and (eq_attr "type" "fpload")
       (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
  3 1)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "load")
       (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
  2 1)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "store,fpstore")
       (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
  1 1)

(define_function_unit "fpu" 1 0
  (and (eq_attr "type" "fpstore")
       (eq_attr "cpu" "rios1,ppc601"))
  0 1)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "fpload")
       (eq_attr "cpu" "rios1"))
  2 1)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "fpload")
       (eq_attr "cpu" "ppc601"))
  3 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "load,fpload")
       (eq_attr "cpu" "rios2"))
  2 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "store,fpstore")
       (eq_attr "cpu" "rios2"))
  1 1)

; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
(define_function_unit "iu" 1 0
  (and (eq_attr "type" "integer")
       (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603"))
  1 1)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601"))
  1 1)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul,imul2,imul3")
       (eq_attr "cpu" "ppc403"))
  4 4)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "ppc405"))
  4 3)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul2,imul3")
       (eq_attr "cpu" "ppc405"))
  3 2)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "rios1"))
  5 5)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul2")
       (eq_attr "cpu" "rios1"))
  4 4)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul3")
       (eq_attr "cpu" "rios1"))
  3 3)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul,imul2,imul3")
       (eq_attr "cpu" "ppc601,ppc603"))
  5 5)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "rs64a"))
  20 20)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul2")
       (eq_attr "cpu" "rs64a"))
  12 12)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "imul3")
       (eq_attr "cpu" "rs64a"))
  8 8)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "lmul")
       (eq_attr "cpu" "rs64a"))
  34 34)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "rios1"))
  19 19)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "rs64a"))
  66 66)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "ldiv")
       (eq_attr "cpu" "rs64a"))
  66 66)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc403"))
  33 33)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc405"))
  35 35)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc601"))
  36 36)

(define_function_unit "iu" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc603"))
  37 36)

; RIOS2 has two integer units: a primary one which can perform all
; operations and a secondary one which is fed in lock step with the first
; and can perform "simple" integer operations.  
; To catch this we define a 'dummy' imuldiv-unit that is also needed
; for the complex insns. 
(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "integer")
       (eq_attr "cpu" "rios2"))
  1 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "imul,imul2,imul3")
       (eq_attr "cpu" "rios2"))
  2 2)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "rios2"))
  13 13)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul,imul2,imul3")
       (eq_attr "cpu" "rios2"))
  2 2)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "rios2"))
  13 13)

; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
; Divide latency varies greatly from 2-11, use 6 as average
(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul,imul2,imul3")
       (eq_attr "cpu" "mpccore"))
  2 1)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "mpccore"))
  6 6)

; PPC604{,e} has two units that perform integer operations
; and one unit for divide/multiply operations (and move
; from/to spr).
(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "integer")
       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
  1 1)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul,imul2,imul3")
       (eq_attr "cpu" "ppc604"))
  4 2)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul,imul2,imul3")
       (eq_attr "cpu" "ppc604e"))
  2 1)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "ppc620,ppc630"))
  5 3)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul2")
       (eq_attr "cpu" "ppc620,ppc630"))
  4 3)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul3")
       (eq_attr "cpu" "ppc620,ppc630"))
  3 3)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "lmul")
       (eq_attr "cpu" "ppc620,ppc630"))
  7 5)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc604,ppc604e"))
  20 19)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc620"))
  37 36)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc630"))
  21 20)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "ldiv")
       (eq_attr "cpu" "ppc620,ppc630"))
  37 36)

; PPC7450 has 3 integer units (for most integer insns) and one mul/div
; unit, which also does CR-logical insns and move to/from SPR.
; It also has 4 vector units, one for each type of vector instruction.
; However, we can only dispatch 2 instructions per cycle. 
; We model this as saying that dispatching two of the same type of instruction
; in a row incurs a single cycle delay.
(define_function_unit "iu3" 3 0
  (and (eq_attr "type" "integer")
       (eq_attr "cpu" "ppc7450"))
  1 1)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "ppc7450"))
  4 2)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul2,imul3")
       (eq_attr "cpu" "ppc7450"))
  3 1)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc7450"))
  23 23)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "cr_logical")
       (eq_attr "cpu" "ppc7450"))
  1 1)

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "vecsimple")
       (eq_attr "cpu" "ppc7450"))
  1 2 [(eq_attr "type" "vecsimple")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "vecsimple")
       (eq_attr "cpu" "ppc7450"))
  1 1 [(eq_attr "type" "!vecsimple")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "veccomplex")
       (eq_attr "cpu" "ppc7450"))
  4 2 [(eq_attr "type" "veccomplex")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "veccomplex")
       (eq_attr "cpu" "ppc7450"))
  4 1 [(eq_attr "type" "!veccomplex")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "veccmp")
       (eq_attr "cpu" "ppc7450"))
  2 2 [(eq_attr "type" "veccmp")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "veccmp")
       (eq_attr "cpu" "ppc7450"))
  2 1 [(eq_attr "type" "!veccmp")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "vecfloat")
       (eq_attr "cpu" "ppc7450"))
  4 2 [(eq_attr "type" "vecfloat")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "vecfloat")
       (eq_attr "cpu" "ppc7450"))
  4 1 [(eq_attr "type" "!vecfloat")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "vecperm")
       (eq_attr "cpu" "ppc7450"))
  2 2 [(eq_attr "type" "vecperm")])

(define_function_unit "vec_alu2" 2 0
  (and (eq_attr "type" "vecperm")
       (eq_attr "cpu" "ppc7450"))
  2 1 [(eq_attr "type" "!vecperm")])

; PPC750 has two integer units: a primary one which can perform all
; operations and a secondary one which is fed in lock step with the first
; and can perform "simple" integer operations.  
; To catch this we define a 'dummy' imuldiv-unit that is also needed
; for the complex insns. 
(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "integer")
       (eq_attr "cpu" "ppc750,ppc7400"))
  1 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "ppc750,ppc7400"))
  4 4)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "imul2")
       (eq_attr "cpu" "ppc750,ppc7400"))
  3 2)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "imul3")
       (eq_attr "cpu" "ppc750,ppc7400"))
  2 1)

(define_function_unit "iu2" 2 0
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc750,ppc7400"))
  19 19)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul")
       (eq_attr "cpu" "ppc750,ppc7400"))
  4 4)

(define_function_unit "imuldiv" 1 0
  (and (eq_attr "type" "imul2")