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linux下的gcc编译器

})

(define_expand "unaligned_extendhidi_be"
  [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
   (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
   (set (match_dup 4)
	(mem:DI (and:DI (match_dup 3)
			(const_int -8))))
   (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
   (set (match_dup 6)
	(ashift:DI (match_dup 4)
		   (ashift:DI
		     (and:DI
		       (plus:DI (match_dup 5) (const_int 1))
		       (const_int 7))
		     (const_int 3))))
   (set (match_operand:DI 0 "register_operand" "")
	(ashiftrt:DI (match_dup 6) (const_int 48)))]
  "WORDS_BIG_ENDIAN"
{
  operands[2] = gen_reg_rtx (DImode);
  operands[3] = gen_reg_rtx (DImode);
  operands[4] = gen_reg_rtx (DImode);
  operands[5] = gen_reg_rtx (DImode);
  operands[6] = gen_reg_rtx (DImode);
})

(define_insn "*extxl_const"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
			 (match_operand:DI 2 "mode_width_operand" "n")
			 (match_operand:DI 3 "mul8_operand" "I")))]
  ""
  "ext%M2l %r1,%s3,%0"
  [(set_attr "type" "shift")])

(define_insn "extxl_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
			 (match_operand:DI 2 "mode_width_operand" "n")
			 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
				    (const_int 3))))]
  "! WORDS_BIG_ENDIAN"
  "ext%M2l %r1,%3,%0"
  [(set_attr "type" "shift")])

(define_insn "extxl_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
			 (match_operand:DI 2 "mode_width_operand" "n")
			 (minus:DI
			   (const_int 56)
			   (ashift:DI
			     (match_operand:DI 3 "reg_or_8bit_operand" "rI")
			     (const_int 3)))))]
  "WORDS_BIG_ENDIAN"
  "ext%M2l %r1,%3,%0"
  [(set_attr "type" "shift")])

;; Combine has some strange notion of preserving existing undefined behavior
;; in shifts larger than a word size.  So capture these patterns that it
;; should have turned into zero_extracts.

(define_insn "*extxl_1_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
		  (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
			     (const_int 3)))
	     (match_operand:DI 3 "mode_mask_operand" "n")))]
  "! WORDS_BIG_ENDIAN"
  "ext%U3l %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "*extxl_1_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI (lshiftrt:DI
		  (match_operand:DI 1 "reg_or_0_operand" "rJ")
		  (minus:DI (const_int 56)
		    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
			       (const_int 3))))
		(match_operand:DI 3 "mode_mask_operand" "n")))]
  "WORDS_BIG_ENDIAN"
  "ext%U3l %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "*extql_2_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
	  (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		     (const_int 3))))]
  "! WORDS_BIG_ENDIAN"
  "extql %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "*extql_2_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lshiftrt:DI
	  (match_operand:DI 1 "reg_or_0_operand" "rJ")
	  (minus:DI (const_int 56)
		    (ashift:DI
		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		      (const_int 3)))))]
  "WORDS_BIG_ENDIAN"
  "extql %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "extqh_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI
	 (match_operand:DI 1 "reg_or_0_operand" "rJ")
	  (minus:DI (const_int 64)
		    (ashift:DI
		     (and:DI
		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		      (const_int 7))
		     (const_int 3)))))]
  "! WORDS_BIG_ENDIAN"
  "extqh %r1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "extqh_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI
	  (match_operand:DI 1 "reg_or_0_operand" "rJ")
	  (ashift:DI
	    (and:DI
	      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		       (const_int 1))
	      (const_int 7))
	    (const_int 3))))]
  "WORDS_BIG_ENDIAN"
  "extqh %r1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "extlh_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI
	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
		 (const_int 2147483647))
	 (minus:DI (const_int 64)
		    (ashift:DI
		     (and:DI
		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		      (const_int 7))
		     (const_int 3)))))]
  "! WORDS_BIG_ENDIAN"
  "extlh %r1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "extlh_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI
	  (ashift:DI
	    (match_operand:DI 1 "reg_or_0_operand" "rJ")
	    (ashift:DI
	      (and:DI
		(plus:DI
		  (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		  (const_int 1))
		(const_int 7))
	      (const_int 3)))
	  (const_int 2147483647)))]
  "WORDS_BIG_ENDIAN"
  "extlh %r1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "extwh_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI
	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
		 (const_int 65535))
	 (minus:DI (const_int 64)
		    (ashift:DI
		     (and:DI
		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		      (const_int 7))
		     (const_int 3)))))]
  "! WORDS_BIG_ENDIAN"
  "extwh %r1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "extwh_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI
	  (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
		     (ashift:DI
		       (and:DI
			 (plus:DI
			   (match_operand:DI 2 "reg_or_8bit_operand" "rI")
			   (const_int 1))
			 (const_int 7))
		       (const_int 3)))
	  (const_int 65535)))]
  "WORDS_BIG_ENDIAN"
  "extwh %r1,%2,%0"
  [(set_attr "type" "shift")])

;; This converts an extXl into an extXh with an appropriate adjustment
;; to the address calculation.

;;(define_split
;;  [(set (match_operand:DI 0 "register_operand" "")
;;	(ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
;;				    (match_operand:DI 2 "mode_width_operand" "")
;;				    (ashift:DI (match_operand:DI 3 "" "")
;;					       (const_int 3)))
;;		   (match_operand:DI 4 "const_int_operand" "")))
;;   (clobber (match_operand:DI 5 "register_operand" ""))]
;;  "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
;;  [(set (match_dup 5) (match_dup 6))
;;   (set (match_dup 0)
;;	(ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
;;				    (ashift:DI (plus:DI (match_dup 5)
;;							(match_dup 7))
;;					       (const_int 3)))
;;		   (match_dup 4)))]
;;  "
;;{
;;  operands[6] = plus_constant (operands[3],
;;			       INTVAL (operands[2]) / BITS_PER_UNIT);
;;  operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
;;}")

(define_insn "*insbl_const"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
		   (match_operand:DI 2 "mul8_operand" "I")))]
  ""
  "insbl %1,%s2,%0"
  [(set_attr "type" "shift")])

(define_insn "*inswl_const"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
		   (match_operand:DI 2 "mul8_operand" "I")))]
  ""
  "inswl %1,%s2,%0"
  [(set_attr "type" "shift")])

(define_insn "*insll_const"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
		   (match_operand:DI 2 "mul8_operand" "I")))]
  ""
  "insll %1,%s2,%0"
  [(set_attr "type" "shift")])

(define_insn "insbl_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
			      (const_int 3))))]
  "! WORDS_BIG_ENDIAN"
  "insbl %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "insbl_be"
 [(set (match_operand:DI 0 "register_operand" "=r")
       (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
	 (minus:DI (const_int 56)
	   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		      (const_int 3)))))]
  "WORDS_BIG_ENDIAN"
  "insbl %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "inswl_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
			      (const_int 3))))]
  "! WORDS_BIG_ENDIAN"
  "inswl %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "inswl_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
	  (minus:DI (const_int 56)
	    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		       (const_int 3)))))]
  "WORDS_BIG_ENDIAN"
  "inswl %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "insll_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
			      (const_int 3))))]
  "! WORDS_BIG_ENDIAN"
  "insll %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "insll_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
	  (minus:DI (const_int 56)
	    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		       (const_int 3)))))]
  "WORDS_BIG_ENDIAN"
  "insll %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "insql_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (match_operand:DI 1 "register_operand" "r")
		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
			      (const_int 3))))]
  "! WORDS_BIG_ENDIAN"
  "insql %1,%2,%0"
  [(set_attr "type" "shift")])

(define_insn "insql_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (match_operand:DI 1 "register_operand" "r")
	  (minus:DI (const_int 56)
	    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
		       (const_int 3)))))]
  "WORDS_BIG_ENDIAN"
  "insql %1,%2,%0"
  [(set_attr "type" "shift")])

;; Combine has this sometimes habit of moving the and outside of the
;; shift, making life more interesting.

(define_insn "*insxl"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
		   	   (match_operand:DI 2 "mul8_operand" "I"))
		(match_operand:DI 3 "immediate_operand" "i")))]
  "HOST_BITS_PER_WIDE_INT == 64
   && GET_CODE (operands[3]) == CONST_INT
   && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
        == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
       || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
        == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
       || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
        == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
{
#if HOST_BITS_PER_WIDE_INT == 64
  if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
      == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
    return "insbl %1,%s2,%0";
  if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
      == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
    return "inswl %1,%s2,%0";
  if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
      == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
    return "insll %1,%s2,%0";
#endif
  abort();
}
  [(set_attr "type" "shift")])

;; We do not include the insXh insns because they are complex to express
;; and it does not appear that we would ever want to generate them.
;;
;; Since we need them for block moves, though, cop out and use unspec.

(define_insn "insxh"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand:DI 1 "register_operand" "r")
		    (match_operand:DI 2 "mode_width_operand" "n")
		    (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
		   UNSPEC_INSXH))]
  ""
  "ins%M2h %1,%3,%0"
  [(set_attr "type" "shift")])

(define_insn "mskxl_le"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI (not:DI (ashift:DI
			 (match_operand:DI 2 "mode_mask_operand" "n")
			 (ashift:DI
			  (match_operand:DI 3 "reg_or_8bit_operand" "rI")
			  (const_int 3))))
		(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
  "! WORDS_BIG_ENDIAN"
  "msk%U2l %r1,%3,%0"
  [(set_attr "type" "shift")])

(define_insn "mskxl_be"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI (not:DI (ashift:DI
			  (match_operand:DI 2 "mode_mask_operand" "n")
			  (minus:DI (const_int 56)
			    (ashift:DI
			      (match_operand:DI 3 "reg_or_8bit_operand" "rI")
			      (const_int 3)))))
		(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
  "WORDS_BIG_ENDIAN"
  "msk%U2l %r1,%3,%0"
  [(set_attr "type" "shift")])

;; We do not include the mskXh insns because it does not appear we would
;; ever generate one.
;;
;; Again, we do for block moves and we use unspec again.

(define_insn "mskxh"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(unspec:DI [(match_operand:DI 1 "register_operand" "r")
		    (match_operand:DI 2 "mode_width_operand" "n")
		    (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
		   UNSPEC_MSKXH))]
  ""
  "msk%M2h %1,%3,%0"
  [(set_attr "type" "shift")])

;; Prefer AND + NE over LSHIFTRT + AND.

(define_insn_and_split "*ze_and_ne"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
			 (const_int 1)
			 (match