alpha.md

linux下的gcc编译器

   (parallel [(set (match_dup 5)
		   (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
	      (clobber (reg:DI 23))
	      (clobber (reg:DI 28))])
   (set (match_operand:SI 0 "nonimmediate_operand" "")
	(subreg:SI (match_dup 5) 0))]
  "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
{
  operands[3] = gen_reg_rtx (DImode);
  operands[4] = gen_reg_rtx (DImode);
  operands[5] = gen_reg_rtx (DImode);
})

(define_expand "divdi3"
  [(parallel [(set (match_operand:DI 0 "register_operand" "")
		   (div:DI (match_operand:DI 1 "register_operand" "")
			   (match_operand:DI 2 "register_operand" "")))
	      (clobber (reg:DI 23))
	      (clobber (reg:DI 28))])]
  "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
  "")

(define_expand "udivdi3"
  [(parallel [(set (match_operand:DI 0 "register_operand" "")
		   (udiv:DI (match_operand:DI 1 "register_operand" "")
			    (match_operand:DI 2 "register_operand" "")))
	      (clobber (reg:DI 23))
	      (clobber (reg:DI 28))])]
  "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
  "")

(define_expand "moddi3"
  [(use (match_operand:DI 0 "register_operand" ""))
   (use (match_operand:DI 1 "register_operand" ""))
   (use (match_operand:DI 2 "register_operand" ""))]
  "!TARGET_ABI_OPEN_VMS"
{
  if (TARGET_ABI_UNICOSMK)
    emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
  DONE;
})

(define_expand "moddi3_dft"
  [(parallel [(set (match_operand:DI 0 "register_operand" "")
		   (mod:DI (match_operand:DI 1 "register_operand" "")
			   (match_operand:DI 2 "register_operand" "")))
	      (clobber (reg:DI 23))
	      (clobber (reg:DI 28))])]
  "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
  "")

;; On Unicos/Mk, we do as the system's C compiler does:
;; compute the quotient, multiply and subtract.

(define_expand "moddi3_umk"
  [(use (match_operand:DI 0 "register_operand" ""))
   (use (match_operand:DI 1 "register_operand" ""))
   (use (match_operand:DI 2 "register_operand" ""))]
  "TARGET_ABI_UNICOSMK"
{
  rtx div, mul = gen_reg_rtx (DImode);

  div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
		      NULL_RTX, 0, OPTAB_LIB);
  div = force_reg (DImode, div);
  emit_insn (gen_muldi3 (mul, operands[2], div));
  emit_insn (gen_subdi3 (operands[0], operands[1], mul));
  DONE;
})

(define_expand "umoddi3"
  [(use (match_operand:DI 0 "register_operand" ""))
   (use (match_operand:DI 1 "register_operand" ""))
   (use (match_operand:DI 2 "register_operand" ""))]
  "! TARGET_ABI_OPEN_VMS"
{
  if (TARGET_ABI_UNICOSMK)
    emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
  DONE;
})

(define_expand "umoddi3_dft"
  [(parallel [(set (match_operand:DI 0 "register_operand" "")
		   (umod:DI (match_operand:DI 1 "register_operand" "")
			    (match_operand:DI 2 "register_operand" "")))
	      (clobber (reg:DI 23))
	      (clobber (reg:DI 28))])]
  "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
  "")

(define_expand "umoddi3_umk"
  [(use (match_operand:DI 0 "register_operand" ""))
   (use (match_operand:DI 1 "register_operand" ""))
   (use (match_operand:DI 2 "register_operand" ""))]
  "TARGET_ABI_UNICOSMK"
{
  rtx div, mul = gen_reg_rtx (DImode);

  div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
		      NULL_RTX, 1, OPTAB_LIB);
  div = force_reg (DImode, div);
  emit_insn (gen_muldi3 (mul, operands[2], div));
  emit_insn (gen_subdi3 (operands[0], operands[1], mul));
  DONE;
})

;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
;; expanded by the assembler.

(define_insn_and_split "*divmodsi_internal_er"
  [(set (match_operand:DI 0 "register_operand" "=c")
	(sign_extend:DI (match_operator:SI 3 "divmod_operator"
			[(match_operand:DI 1 "register_operand" "a")
			 (match_operand:DI 2 "register_operand" "b")])))
   (clobber (reg:DI 23))
   (clobber (reg:DI 28))]
  "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
  "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
  "&& reload_completed"
  [(parallel [(set (match_dup 0)
		   (sign_extend:DI (match_dup 3)))
	      (use (match_dup 0))
	      (use (match_dup 4))
	      (clobber (reg:DI 23))
	      (clobber (reg:DI 28))])]
{
  const char *str;
  switch (GET_CODE (operands[3]))
    {
    case DIV: 
      str = "__divl";
      break; 
    case UDIV:
      str = "__divlu";
      break;
    case MOD:
      str = "__reml";
      break;
    case UMOD:
      str = "__remlu";
      break;
    default:
      abort ();
    }
  operands[4] = GEN_INT (alpha_next_sequence_number++);
  emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
				  gen_rtx_SYMBOL_REF (DImode, str),
				  operands[4]));
}
  [(set_attr "type" "jsr")
   (set_attr "length" "8")])

(define_insn "*divmodsi_internal_er_1"
  [(set (match_operand:DI 0 "register_operand" "=c")
	(sign_extend:DI (match_operator:SI 3 "divmod_operator"
                        [(match_operand:DI 1 "register_operand" "a")
                         (match_operand:DI 2 "register_operand" "b")])))
   (use (match_operand:DI 4 "register_operand" "c"))
   (use (match_operand 5 "const_int_operand" ""))
   (clobber (reg:DI 23))
   (clobber (reg:DI 28))]
  "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
  "jsr $23,($27),__%E3%J5"
  [(set_attr "type" "jsr")
   (set_attr "length" "4")])

(define_insn "*divmodsi_internal"
  [(set (match_operand:DI 0 "register_operand" "=c")
	(sign_extend:DI (match_operator:SI 3 "divmod_operator"
			[(match_operand:DI 1 "register_operand" "a")
			 (match_operand:DI 2 "register_operand" "b")])))
   (clobber (reg:DI 23))
   (clobber (reg:DI 28))]
  "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
  "%E3 %1,%2,%0"
  [(set_attr "type" "jsr")
   (set_attr "length" "8")])

(define_insn_and_split "*divmoddi_internal_er"
  [(set (match_operand:DI 0 "register_operand" "=c")
	(match_operator:DI 3 "divmod_operator"
			[(match_operand:DI 1 "register_operand" "a")
			 (match_operand:DI 2 "register_operand" "b")]))
   (clobber (reg:DI 23))
   (clobber (reg:DI 28))]
  "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
  "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
  "&& reload_completed"
  [(parallel [(set (match_dup 0) (match_dup 3))
	      (use (match_dup 0))
	      (use (match_dup 4))
	      (clobber (reg:DI 23))
	      (clobber (reg:DI 28))])]
{
  const char *str;
  switch (GET_CODE (operands[3]))
    {
    case DIV: 
      str = "__divq";
      break; 
    case UDIV:
      str = "__divqu";
      break;
    case MOD:
      str = "__remq";
      break;
    case UMOD:
      str = "__remqu";
      break;
    default:
      abort ();
    }
  operands[4] = GEN_INT (alpha_next_sequence_number++);
  emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
				  gen_rtx_SYMBOL_REF (DImode, str),
				  operands[4]));
}
  [(set_attr "type" "jsr")
   (set_attr "length" "8")])

(define_insn "*divmoddi_internal_er_1"
  [(set (match_operand:DI 0 "register_operand" "=c")
	(match_operator:DI 3 "divmod_operator"
                        [(match_operand:DI 1 "register_operand" "a")
                         (match_operand:DI 2 "register_operand" "b")]))
   (use (match_operand:DI 4 "register_operand" "c"))
   (use (match_operand 5 "const_int_operand" ""))
   (clobber (reg:DI 23))
   (clobber (reg:DI 28))]
  "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
  "jsr $23,($27),__%E3%J5"
  [(set_attr "type" "jsr")
   (set_attr "length" "4")])

(define_insn "*divmoddi_internal"
  [(set (match_operand:DI 0 "register_operand" "=c")
	(match_operator:DI 3 "divmod_operator"
			[(match_operand:DI 1 "register_operand" "a")
			 (match_operand:DI 2 "register_operand" "b")]))
   (clobber (reg:DI 23))
   (clobber (reg:DI 28))]
  "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
  "%E3 %1,%2,%0"
  [(set_attr "type" "jsr")
   (set_attr "length" "8")])

;; Next are the basic logical operations.  These only exist in DImode.

(define_insn "anddi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
	(and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
		(match_operand:DI 2 "and_operand" "rI,N,MH")))]
  ""
  "@
   and %r1,%2,%0
   bic %r1,%N2,%0
   zapnot %r1,%m2,%0"
  [(set_attr "type" "ilog,ilog,shift")])

;; There are times when we can split an AND into two AND insns.  This occurs
;; when we can first clear any bytes and then clear anything else.  For
;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
;; Only do this when running on 64-bit host since the computations are
;; too messy otherwise.

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
	(and:DI (match_operand:DI 1 "register_operand" "")
		(match_operand:DI 2 "const_int_operand" "")))]
  "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
  [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
   (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
{
  unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
  unsigned HOST_WIDE_INT mask2 = mask1;
  int i;

  /* For each byte that isn't all zeros, make it all ones.  */
  for (i = 0; i < 64; i += 8)
    if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
      mask1 |= (HOST_WIDE_INT) 0xff << i;

  /* Now turn on any bits we've just turned off.  */
  mask2 |= ~ mask1;

  operands[3] = GEN_INT (mask1);
  operands[4] = GEN_INT (mask2);
})

(define_expand "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
{
  if (! TARGET_BWX)
    operands[1] = force_reg (QImode, operands[1]);
})

(define_insn "*zero_extendqihi2_bwx"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
  "TARGET_BWX"
  "@
   and %1,0xff,%0
   ldbu %0,%1"
  [(set_attr "type" "ilog,ild")])

(define_insn "*zero_extendqihi2_nobwx"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
  "! TARGET_BWX"
  "and %1,0xff,%0"
  [(set_attr "type" "ilog")])

(define_expand "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
{
  if (! TARGET_BWX)
    operands[1] = force_reg (QImode, operands[1]);
})

(define_insn "*zero_extendqisi2_bwx"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
  "TARGET_BWX"
  "@
   and %1,0xff,%0
   ldbu %0,%1"
  [(set_attr "type" "ilog,ild")])

(define_insn "*zero_extendqisi2_nobwx"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
  "! TARGET_BWX"
  "and %1,0xff,%0"
  [(set_attr "type" "ilog")])

(define_expand "zero_extendqidi2"
  [(set (match_operand:DI 0 "register_operand" "")
	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
{
  if (! TARGET_BWX)
    operands[1] = force_reg (QImode, operands[1]);
})

(define_insn "*zero_extendqidi2_bwx"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
  "TARGET_BWX"
  "@
   and %1,0xff,%0
   ldbu %0,%1"
  [(set_attr "type" "ilog,ild")])

(define_insn "*zero_extendqidi2_nobwx"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
  "! TARGET_BWX"
  "and %1,0xff,%0"
  [(set_attr "type" "ilog")])

(define_expand "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
  ""
{
  if (! TARGET_BWX)
    operands[1] = force_reg (HImode, operands[1]);
})

(define_insn "*zero_extendhisi2_bwx"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
  "TARGET_BWX"
  "@
   zapnot %1,3,%0
   ldwu %0,%1"
  [(set_attr "type" "shift,ild")])

(define_insn "*zero_extendhisi2_nobwx"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
  "! TARGET_BWX"
  "zapnot %1,3,%0"
  [(set_attr "type" "shift")])

(define_expand "zero_extendhidi2"
  [(set (match_operand:DI 0 "register_operand" "")
	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
  ""
{
  if (! TARGET_BWX)
    operands[1] = force_reg (HImode, operands[1]);
})

(define_insn "*zero_extendhidi2_bwx"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
  "TARGET_BWX"
  "@
   zapnot %1,3,%0
   ldwu %0,%1"
  [(set_attr "type" "shift,ild")])

(define_insn "*zero_extendhidi2_nobwx"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
  ""
  "zapnot %1,3,%0"
  [(set_attr "type" "shift")])

(define_insn "zero_extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=r")