alpha.md

linux下的gcc编译器

;; Machine description for DEC Alpha for GNU C compiler
;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
;; 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
;; Contributed by Richard Kenner ([e-mail])
;;
;; This file is part of GNU CC.
;;
;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;; Uses of UNSPEC in this file:

(define_constants
  [(UNSPEC_ARG_HOME	0)
   (UNSPEC_CTTZ		1)
   (UNSPEC_INSXH	2)
   (UNSPEC_MSKXH	3)
   (UNSPEC_CVTQL	4)
   (UNSPEC_CVTLQ	5)
   (UNSPEC_UMK_LAUM	6)
   (UNSPEC_UMK_LALM	7)
   (UNSPEC_UMK_LAL	8)
   (UNSPEC_UMK_LOAD_CIW	9)
   (UNSPEC_LDGP2	10)
   (UNSPEC_LITERAL	11)
   (UNSPEC_LITUSE	12)
   (UNSPEC_SIBCALL	13)
   (UNSPEC_SYMBOL	14)

   ;; TLS Support
   (UNSPEC_TLSGD_CALL	15)
   (UNSPEC_TLSLDM_CALL	16)
   (UNSPEC_TLSGD	17)
   (UNSPEC_TLSLDM	18)
   (UNSPEC_DTPREL	19)
   (UNSPEC_TPREL	20)
   (UNSPEC_TP		21)

   ;; Builtins
   (UNSPEC_CMPBGE	22)
   (UNSPEC_ZAP		23)
   (UNSPEC_AMASK	24)
   (UNSPEC_IMPLVER	25)
   (UNSPEC_PERR		26)
   (UNSPEC_CTLZ		27)
   (UNSPEC_CTPOP	28)

   ;; Legacy
   (UNSPEC_NT_LDA	29)
  ])

;; UNSPEC_VOLATILE:

(define_constants
  [(UNSPECV_IMB		0)
   (UNSPECV_BLOCKAGE	1)
   (UNSPECV_SETJMPR	2)	; builtin_setjmp_receiver
   (UNSPECV_LONGJMP	3)	; builtin_longjmp
   (UNSPECV_TRAPB	4)
   (UNSPECV_PSPL	5)	; prologue_stack_probe_loop
   (UNSPECV_REALIGN	6)
   (UNSPECV_EHR		7)	; exception_receiver
   (UNSPECV_MCOUNT	8)
   (UNSPECV_FORCE_MOV	9)
   (UNSPECV_LDGP1	10)
   (UNSPECV_PLDGP2	11)	; prologue ldgp
   (UNSPECV_SET_TP	12)
   (UNSPECV_RPCC	13)
   (UNSPECV_SETJMPR_ER	14)	; builtin_setjmp_receiver fragment
  ])

;; Where necessary, the suffixes _le and _be are used to distinguish between
;; little-endian and big-endian patterns.
;;
;; Note that the Unicos/Mk assembler does not support the following
;; opcodes: mov, fmov, nop, fnop, unop.

;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in alpha.h.

(define_attr "cpu" "ev4,ev5,ev6"
  (const (symbol_ref "alpha_cpu")))

;; Define an insn type attribute.  This is used in function unit delay
;; computations, among other purposes.  For the most part, we use the names
;; defined in the EV4 documentation, but add a few that we have to know about
;; separately.

(define_attr "type"
  "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
  (const_string "iadd"))

;; Describe a user's asm statement.
(define_asm_attributes
  [(set_attr "type" "multi")])

;; Define the operand size an insn operates on.  Used primarily by mul
;; and div operations that have size dependent timings.

(define_attr "opsize" "si,di,udi"
  (const_string "di"))

;; The TRAP attribute marks instructions that may generate traps
;; (which are imprecise and may need a trapb if software completion
;; is desired).

(define_attr "trap" "no,yes"
  (const_string "no"))

;; The ROUND_SUFFIX attribute marks which instructions require a
;; rounding-mode suffix.  The value NONE indicates no suffix,
;; the value NORMAL indicates a suffix controled by alpha_fprm.

(define_attr "round_suffix" "none,normal,c"
  (const_string "none"))

;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
;;   NONE	no suffix
;;   SU		accepts only /su (cmpt et al)
;;   SUI	accepts only /sui (cvtqt and cvtqs)
;;   V_SV	accepts /v and /sv (cvtql only)
;;   V_SV_SVI	accepts /v, /sv and /svi (cvttq only)
;;   U_SU_SUI	accepts /u, /su and /sui (most fp instructions)
;;
;; The actual suffix emitted is controled by alpha_fptm.

(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
  (const_string "none"))

;; The length of an instruction sequence in bytes.

(define_attr "length" ""
  (const_int 4))

;; The USEGP attribute marks instructions that have relocations that use
;; the GP.

(define_attr "usegp" "no,yes"
  (cond [(eq_attr "type" "ldsym,jsr")
	   (const_string "yes")
	 (eq_attr "type" "ild,fld,ist,fst")
	   (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
	]
	(const_string "no")))


;; Include scheduling descriptions.
  
(include "ev4.md")
(include "ev5.md")
(include "ev6.md")

;; First define the arithmetic insns.  Note that the 32-bit forms also
;; sign-extend.

;; Handle 32-64 bit extension from memory to a floating point register
;; specially, since this occurs frequently in int->double conversions.
;;
;; Note that while we must retain the =f case in the insn for reload's
;; benefit, it should be eliminated after reload, so we should never emit
;; code for that case.  But we don't reject the possibility.

(define_expand "extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "")
	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
  ""
  "")

(define_insn "*cvtlq"
  [(set (match_operand:DI 0 "register_operand" "=f")
	(unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
		   UNSPEC_CVTLQ))]
  ""
  "cvtlq %1,%0"
  [(set_attr "type" "fadd")])

(define_insn "*extendsidi2_1"
  [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
	(sign_extend:DI
	  (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
  ""
  "@
   addl $31,%1,%0
   ldl %0,%1
   lds %0,%1\;cvtlq %0,%0"
  [(set_attr "type" "iadd,ild,fld")
   (set_attr "length" "*,*,8")])

(define_split
  [(set (match_operand:DI 0 "hard_fp_register_operand" "")
	(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 1))
   (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
{
  operands[1] = adjust_address (operands[1], SFmode, 0);
  operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
})

;; Optimize sign-extension of SImode loads.  This shows up in the wake of
;; reload when converting fp->int.

(define_peephole2
  [(set (match_operand:SI 0 "hard_int_register_operand" "")
        (match_operand:SI 1 "memory_operand" ""))
   (set (match_operand:DI 2 "hard_int_register_operand" "")
        (sign_extend:DI (match_dup 0)))]
  "true_regnum (operands[0]) == true_regnum (operands[2])
   || peep2_reg_dead_p (2, operands[0])"
  [(set (match_dup 2)
	(sign_extend:DI (match_dup 1)))]
  "")

;; Don't say we have addsi3 if optimizing.  This generates better code.  We
;; have the anonymous addsi3 pattern below in case combine wants to make it.
(define_expand "addsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
		 (match_operand:SI 2 "add_operand" "")))]
  "! optimize"
  "")

(define_insn "*addsi_internal"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
		 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
  ""
  "@
   addl %r1,%2,%0
   subl %r1,%n2,%0
   lda %0,%2(%r1)
   ldah %0,%h2(%r1)")

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_operand:SI 1 "register_operand" "")
		 (match_operand:SI 2 "const_int_operand" "")))]
  "! add_operand (operands[2], SImode)"
  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
{
  HOST_WIDE_INT val = INTVAL (operands[2]);
  HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
  HOST_WIDE_INT rest = val - low;

  operands[3] = GEN_INT (rest);
  operands[4] = GEN_INT (low);
})

(define_insn "*addsi_se"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(sign_extend:DI
	 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
		  (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
  ""
  "@
   addl %r1,%2,%0
   subl %r1,%n2,%0")

(define_insn "*addsi_se2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(sign_extend:DI
	 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
			     (match_operand:DI 2 "sext_add_operand" "rI,O"))
		    0)))]
  ""
  "@
   addl %r1,%2,%0
   subl %r1,%n2,%0")

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
	(sign_extend:DI
	 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
		  (match_operand:SI 2 "const_int_operand" ""))))
   (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
  "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
   && INTVAL (operands[2]) % 4 == 0"
  [(set (match_dup 3) (match_dup 4))
   (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
							(match_dup 5))
					       (match_dup 1))))]
{
  HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
  int mult = 4;

  if (val % 2 == 0)
    val /= 2, mult = 8;

  operands[4] = GEN_INT (val);
  operands[5] = GEN_INT (mult);
})

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
	(sign_extend:DI
	 (plus:SI (match_operator:SI 1 "comparison_operator"
				     [(match_operand 2 "" "")
				      (match_operand 3 "" "")])
		  (match_operand:SI 4 "add_operand" ""))))
   (clobber (match_operand:DI 5 "register_operand" ""))]
  ""
  [(set (match_dup 5) (match_dup 6))
   (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
{
  operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
				operands[2], operands[3]);
  operands[7] = gen_lowpart (SImode, operands[5]);
})

(define_insn "addvsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
		 (match_operand:SI 2 "sext_add_operand" "rI,O")))
   (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
			 (sign_extend:DI (match_dup 2)))
		(sign_extend:DI (plus:SI (match_dup 1)
					 (match_dup 2))))
	    (const_int 0))]
  ""
  "@
   addlv %r1,%2,%0
   sublv %r1,%n2,%0")

(define_expand "adddi3"
  [(set (match_operand:DI 0 "register_operand" "")
	(plus:DI (match_operand:DI 1 "register_operand" "")
		 (match_operand:DI 2 "add_operand" "")))]
  ""
  "")

(define_insn "*adddi_er_lo16_dtp"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
  "HAVE_AS_TLS"
  "lda %0,%2(%1)\t\t!dtprel")

(define_insn "*adddi_er_hi32_dtp"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (match_operand:DI 1 "register_operand" "r")
		 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
  "HAVE_AS_TLS"
  "ldah %0,%2(%1)\t\t!dtprelhi")

(define_insn "*adddi_er_lo32_dtp"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
  "HAVE_AS_TLS"
  "lda %0,%2(%1)\t\t!dtprello")

(define_insn "*adddi_er_lo16_tp"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand:DI 2 "tp16_symbolic_operand" "")))]
  "HAVE_AS_TLS"
  "lda %0,%2(%1)\t\t!tprel")

(define_insn "*adddi_er_hi32_tp"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (match_operand:DI 1 "register_operand" "r")
		 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
  "HAVE_AS_TLS"
  "ldah %0,%2(%1)\t\t!tprelhi")

(define_insn "*adddi_er_lo32_tp"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand:DI 2 "tp32_symbolic_operand" "")))]
  "HAVE_AS_TLS"
  "lda %0,%2(%1)\t\t!tprello")

(define_insn "*adddi_er_high_l"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (match_operand:DI 1 "register_operand" "r")
		 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
  "TARGET_EXPLICIT_RELOCS"
  "ldah %0,%2(%1)\t\t!gprelhigh"
  [(set_attr "usegp" "yes")])

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
  "TARGET_EXPLICIT_RELOCS && reload_completed"
  [(set (match_dup 0)
	(plus:DI (match_dup 2) (high:DI (match_dup 1))))]
  "operands[2] = pic_offset_table_rtx;")

;; We used to expend quite a lot of effort choosing addq/subq/lda.
;; With complications like
;;
;;   The NT stack unwind code can't handle a subq to adjust the stack
;;   (that's a bug, but not one we can do anything about).  As of NT4.0 SP3,
;;   the exception handling code will loop if a subq is used and an
;;   exception occurs.
;;
;;   The 19980616 change to emit prologues as RTL also confused some
;;   versions of GDB, which also interprets prologues.  This has been
;;   fixed as of GDB 4.18, but it does not harm to unconditionally
;;   use lda here.
;;
;; and the fact that the three insns schedule exactly the same, it's
;; just not worth the effort.