romp.h

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{					\
  fprintf (FILE, "\t.short 0,0\n");	\
  fprintf (FILE, "\tcau r0,0(r0)\n");	\
  fprintf (FILE, "\toil r0,r0,0\n");	\
  fprintf (FILE, "\tmts r10,r15\n");	\
  fprintf (FILE, "\tst r0,-36(r1)\n");	\
  fprintf (FILE, "\tcau r15,0(r0)\n");	\
  fprintf (FILE, "\toil r15,r15,0\n");	\
  fprintf (FILE, "\tcas r0,r15,r0\n");	\
  fprintf (FILE, "\tls r15,0(r15)\n");	\
  fprintf (FILE, "\tbrx r15\n");	\
  fprintf (FILE, "\tmfs r10,r15\n");	\
}

/* Length in units of the trampoline for entering a nested function.  */

#define TRAMPOLINE_SIZE    36

/* Emit RTL insns to initialize the variable parts of a trampoline.
   FNADDR is an RTX for the address of the function's pure code.
   CXT is an RTX for the static chain value for the function.

   On the RT, the static chain and function addresses are written in
   two 16-bit sections.

   We also need to write the address of the first instruction in
   the trampoline into the first word of the trampoline to simulate a
   data area.  */

#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT)		\
	romp_initialize_trampoline (ADDR, FNADDR, CXT)

/* Definitions for register eliminations.

   We have two registers that can be eliminated on the ROMP.  First, the
   frame pointer register can often be eliminated in favor of the stack
   pointer register.  Secondly, the argument pointer register can always be
   eliminated; it is replaced with either the stack or frame pointer.

   In addition, we use the elimination mechanism to see if r14 is needed.
   Initially we assume that it isn't.  If it is, we spill it.  This is done
   by making it an eliminable register.  It doesn't matter what we replace
   it with, since it will never occur in the rtl at this point.  */

/* This is an array of structures.  Each structure initializes one pair
   of eliminable registers.  The "from" register number is given first,
   followed by "to".  Eliminations of the same "from" register are listed
   in order of preference.  */
#define ELIMINABLE_REGS				\
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
 { 14, 0}}

/* Given FROM and TO register numbers, say whether this elimination is allowed.
   Frame pointer elimination is automatically handled.

   For the ROMP, if frame pointer elimination is being done, we would like to
   convert ap into fp, not sp.

   We need r14 if various conditions (tested in romp_using_r14) are true.

   All other eliminations are valid.  */
#define CAN_ELIMINATE(FROM, TO)					\
 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM	\
  ? ! frame_pointer_needed					\
  : (FROM) == 14 ? ! romp_using_r14 ()				\
  : 1)

/* Define the offset between two registers, one to be eliminated, and the other
   its replacement, at the start of a routine.  */
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
{ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
    {									\
      if (romp_pushes_stack ())						\
	(OFFSET) = ((get_frame_size () - 64)				\
		    + current_function_outgoing_args_size);		\
      else								\
	(OFFSET) = - (romp_sa_size () + 64);				\
    }									\
  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
    (OFFSET) = romp_sa_size () - 16 + 64;				\
  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
    {									\
      if (romp_pushes_stack ())						\
	(OFFSET) = (get_frame_size () + (romp_sa_size () - 16)		\
		    + current_function_outgoing_args_size);		\
      else								\
	(OFFSET) = -16;							\
    }									\
  else if ((FROM) == 14)						\
    (OFFSET) = 0;							\
  else									\
    abort ();								\
}

/* Addressing modes, and classification of registers for them.  */

/* #define HAVE_POST_INCREMENT 0 */
/* #define HAVE_POST_DECREMENT 0 */

/* #define HAVE_PRE_DECREMENT 0 */
/* #define HAVE_PRE_INCREMENT 0 */

/* Macros to check register numbers against specific register classes.  */

/* These assume that REGNO is a hard or pseudo reg number.
   They give nonzero only if REGNO is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   Since they use reg_renumber, they are safe only once reg_renumber
   has been allocated, which happens in local-alloc.c.  */

#define REGNO_OK_FOR_INDEX_P(REGNO) 0
#define REGNO_OK_FOR_BASE_P(REGNO)				\
((REGNO) < FIRST_PSEUDO_REGISTER				\
 ? (REGNO) < 16 && (REGNO) != 0 && (REGNO) != 16		\
 : (reg_renumber[REGNO] < 16 && reg_renumber[REGNO] >= 0	\
    && reg_renumber[REGNO] != 16))

/* Maximum number of registers that can appear in a valid memory address.  */

#define MAX_REGS_PER_ADDRESS 1

/* Recognize any constant value that is a valid address.  */

#define CONSTANT_ADDRESS_P(X)   \
  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
   || GET_CODE (X) == HIGH)

/* Nonzero if the constant value X is a legitimate general operand.
   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.

   On the ROMP, there is a bit of a hack here.  Basically, we wish to
   only issue instructions that are not `as' macros.  However, in the
   case of `get', `load', and `store', if the operand is a relocatable
   symbol (possibly +/- an integer), there is no way to express the
   resulting split-relocation except with the macro.  Therefore, allow
   either a constant valid in a normal (sign-extended) D-format insn or
   a relocatable expression.

   Also, for DFmode and DImode, we must ensure that both words are
   addressable.

   We define two macros: The first is given an offset (0 or 4) and indicates
   that the operand is a CONST_INT that is valid for that offset.  The second
   indicates a valid non-CONST_INT constant.  */

#define LEGITIMATE_ADDRESS_INTEGER_P(X,OFFSET)				\
  (GET_CODE (X) == CONST_INT						\
   && (unsigned) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)

#define LEGITIMATE_ADDRESS_CONSTANT_P(X)				\
 (GET_CODE (X) == SYMBOL_REF						\
  || GET_CODE (X) == LABEL_REF						\
  || (GET_CODE (X) == CONST						\
      && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF		\
          || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)		\
      && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))

/* Include all constant integers and constant double, but exclude 
   SYMBOL_REFs that are to be obtained from the data area (see below).  */
#define LEGITIMATE_CONSTANT_P(X)		\
  ((LEGITIMATE_ADDRESS_CONSTANT_P (X)		\
    || GET_CODE (X) == CONST_INT		\
    || GET_CODE (X) == CONST_DOUBLE)		\
   && ! (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))

/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
   and check its validity for a certain class.
   We have two alternate definitions for each of them.
   The usual definition accepts all pseudo regs; the other rejects
   them unless they have been allocated suitable hard regs.
   The symbol REG_OK_STRICT causes the latter definition to be used.

   Most source files want to accept pseudo regs in the hope that
   they will get allocated to the class that the insn wants them to be in.
   Source files for reload pass need to be strict.
   After reload, it makes no difference, since pseudo regs have
   been eliminated by then.  */

#ifndef REG_OK_STRICT

/* Nonzero if X is a hard reg that can be used as an index
   or if it is a pseudo reg.  */
#define REG_OK_FOR_INDEX_P(X) 0
/* Nonzero if X is a hard reg that can be used as a base reg
   or if it is a pseudo reg.  */
#define REG_OK_FOR_BASE_P(X)		\
  (REGNO (X) != 0 && (REGNO (X) < 17 || REGNO (X) >= FIRST_PSEUDO_REGISTER))

#else

/* Nonzero if X is a hard reg that can be used as an index.  */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as a base reg.  */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))

#endif

/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
   that is a valid memory address for an instruction.
   The MODE argument is the machine mode for the MEM expression
   that wants to use this address.

   On the ROMP, a legitimate address is either a legitimate constant,
   a register plus a legitimate constant, or a register.  See the
   discussion at the LEGITIMATE_ADDRESS_CONSTANT_P macro.  */
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
{ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
    goto ADDR;								\
  if (GET_CODE (X) != CONST_INT && LEGITIMATE_ADDRESS_CONSTANT_P (X))	\
    goto ADDR;								\
  if (GET_CODE (X) == PLUS						\
      && GET_CODE (XEXP (X, 0)) == REG					\
      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
      && LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (X, 1)))			\
	goto ADDR;							\
  if (GET_CODE (X) == PLUS						\
      && GET_CODE (XEXP (X, 0)) == REG					\
      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0)			\
      && (((MODE) != DFmode && (MODE) != DImode)			\
	  || (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4))))		\
	goto ADDR;							\
}

/* Try machine-dependent ways of modifying an illegitimate address
   to be legitimate.  If we find one, return the new, valid address.
   This macro is used in only one place: `memory_address' in explow.c.

   OLDX is the address as it was before break_out_memory_refs was called.
   In some cases it is useful to look at this to decide what needs to be done.

   MODE and WIN are passed so that this macro can use
   GO_IF_LEGITIMATE_ADDRESS.

   It is always safe for this macro to do nothing.  It exists to recognize
   opportunities to optimize the output.

   On ROMP, check for the sum of a register with a constant
   integer that is out of range.  If so, generate code to add the
   constant with the low-order 16 bits masked to the register and force
   this result into another register (this can be done with `cau').
   Then generate an address of REG+(CONST&0xffff), allowing for the 
   possibility of bit 16 being a one.

   If the register is not OK for a base register, abort.  */

#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG	\
    && GET_CODE (XEXP (X, 1)) == CONST_INT			\
    && (unsigned) (INTVAL (XEXP (X, 1)) + 0x8000) >= 0x10000)	\
    { int high_int, low_int;					\
      if (! REG_OK_FOR_BASE_P (XEXP (X, 0)))			\
	abort ();						\
      high_int = INTVAL (XEXP (X, 1)) >> 16;			\
      low_int = INTVAL (XEXP (X, 1)) & 0xffff;			\
      if (low_int & 0x8000)					\
	high_int += 1, low_int |= 0xffff0000;			\
      (X) = gen_rtx_PLUS (SImode,				\
			  force_operand (plus_constant (XEXP (X, 0),  \
							high_int << 16), 0), \
			  GEN_INT (low_int));			\
    }								\
}

/* Go to LABEL if ADDR (a legitimate address expression)
   has an effect that depends on the machine mode it is used for.

   On the ROMP this is true only if the address is valid with a zero offset
   but not with an offset of four (this means it cannot be used as an
   address for DImode or DFmode).  Since we know it is valid, we just check
   for an address that is not valid with an offset of four.  */

#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)		\
{ if (GET_CODE (ADDR) == PLUS					\
      && ! LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (ADDR, 1))	\
      && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 4))	\
    goto LABEL;							\
}

/* Define this if some processing needs to be done immediately before
   emitting code for an insn.

   This is used on the ROMP, to compensate for a bug in the floating-point
   code.  When a floating-point operation is done with the first and third
   operands both the same floating-point register, it will generate bad code
   for the MC68881.  So we must detect this.  If it occurs, we patch the 
   first operand to be fr0 and insert a move insn to move it to the desired
   destination.  */
#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS)			\
  { rtx op0, op1, op2, operation, tem;					\
    if (NOPERANDS >= 3	&& get_attr_type (INSN) == TYPE_FP)		\
      {									\
	op0 = OPERANDS[0];						\
	operation = OPERANDS[1];					\
	if (float_conversion (operation, VOIDmode))			\
	  operation = XEXP (operation, 0);				\
        if (float_binary (operation, VOIDmode))				\
	  {								\
	    op1 = XEXP (operation, 0), op2 = XEXP (operation, 1);	\
	    if (float_conversion (op1, VOIDmode))			\
	      op1 = XEXP (op1, 0);					\
	    if (float_conversion (op2, VOIDmode))			\
	      op2 = XEXP (op2, 0);					\
	    if (rtx_equal_p (op0, op2)					\
		&& (GET_CODE (operation) == PLUS			\
		    || GET_CODE (operation) == MULT))			\
	      tem = op1, op1 = op2, op2 = tem;				\
	    if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0))	\
		&& GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2))	\
		&& REGNO (op0) == REGNO (op2))				\
	      {								\
		tem = gen_rtx_REG (GET_MODE (op0), 17);		\
		emit_insn_after (gen_move_insn (op0, tem), INSN);	\
		SET_DEST (XVECEXP (PATTERN (INSN), 0, 0)) = tem; 	\
		OPERANDS[0] = tem;					\
	      }								\
	  }								\
      }									\
  }

/* Specify the machine mode that this machine uses
   for the index in the tablejump instruction.  */
#define CASE_VECTOR_MODE SImode

/* Define as C expression which evaluates to nonzero if the tablejump
   instruction expects the table to contain offsets from the address of the
   table.
   Do not define this if the table should contain absolute addresses.  */
/* #define CASE_VECTOR_PC_RELATIVE 1 */

/* Define this as 1 if `char' should by default be signed; else as 0.  */
#define DEFAULT_SIGNED_CHAR 0

/* This flag, if defined, says the same insns that convert to a signed fixnum
   also convert validly to an unsigned one.

   We actually lie a bit here as overflow conditions are different.  But
   they aren't being checked anyway.  */

#define FIXUNS_TRUNC_LIKE_FIX_TRUNC

/* Max number of bytes we can move from memory to memory
   in one reasonably fast instruction.  */
#define MOVE_MAX 4

/* Nonzero if access to memory by bytes is no faster than for words.
   Also nonzero if doing byte operations (specifically shifts) in registers
   is undesirable.  */
#define SLOW_BYTE_ACCESS 1

/* Define if operations between registers always perform the operation
   on the full register even if a narrower mode is specified.  */
#define WORD_REGISTER_OPERATIONS

/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
   will either zero-extend or sign-extend.  The value of this macro should
   be the code that says which one of the two operations is implicitly
   done, NIL if none.  */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND

/* This is BSD, so it wants DBX format.  */
#define DBX_DEBUGGING_INFO 1

/* Define the letter code used in a stabs entry for parameters passed
   with the register attribute.