romp.h

linux下的gcc编译器

/* Definitions of target machine for GNU compiler, for ROMP chip.
   Copyright (C) 1989, 1991, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2002
   Free Software Foundation, Inc.
   Contributed by Richard Kenner ([e-mail])

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */


/* Names to predefine in the preprocessor for this target machine.  */

#define CPP_PREDEFINES "-Dibm032 -Dunix -Asystem=unix -Asystem=bsd  -Acpu=ibm032 -Amachine=ibm032"

/* Print subsidiary information on the compiler version in use.  */
#define TARGET_VERSION ;

/* Add -lfp_p when running with -p or -pg.  */
#define LIB_SPEC "%{pg:-lfp_p}%{p:-lfp_p} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"

/* Run-time compilation parameters selecting different hardware subsets.  */

/* Flag to generate all multiplies as an in-line sequence of multiply-step
   insns instead of calling a library routine.  */
#define TARGET_IN_LINE_MUL (target_flags & 1)

/* Flag to generate padded floating-point data blocks.  Otherwise, we generate
   them the minimum size.  This trades off execution speed against size.  */
#define TARGET_FULL_FP_BLOCKS (target_flags & 2)

/* Flag to pass and return floating point values in floating point registers.
   Since this violates the linkage convention, we feel free to destroy fr2
   and fr3 on function calls.
   fr1-fr3 are used to pass the arguments.  */
#define TARGET_FP_REGS (target_flags & 4)

/* Flag to return structures of more than one word in memory.  This is for
   compatibility with the MetaWare HighC (hc) compiler.  */
#define TARGET_HC_STRUCT_RETURN (target_flags & 010)

extern int target_flags;

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES		\
  { {"in-line-mul", 1},		\
    {"call-lib-mul", -1},	\
    {"full-fp-blocks", 2},	\
    {"minimum-fp-blocks", -2},	\
    {"fp-arg-in-fpregs", 4},	\
    {"fp-arg-in-gregs", -4},	\
    {"hc-struct-return", 010},  \
    {"nohc-struct-return", - 010}, \
    { "", TARGET_DEFAULT}}

#define TARGET_DEFAULT 3

/* target machine storage layout */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
/* That is true on ROMP.  */
#define BITS_BIG_ENDIAN 1

/* Define this if most significant byte of a word is the lowest numbered.  */
/* That is true on ROMP.  */
#define BYTES_BIG_ENDIAN 1

/* Define this if most significant word of a multiword number is lowest
   numbered. 

   For ROMP we can decide arbitrarily since there are no machine instructions
   for them.  Might as well be consistent with bits and bytes.  */
#define WORDS_BIG_ENDIAN 1

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 4

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY 32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 32

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 16

/* No data type wants to be aligned rounder than this.  */
#define BIGGEST_ALIGNMENT 32

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 32

/* Every structure's size must be a multiple of this.  */
#define STRUCTURE_SIZE_BOUNDARY 8

/* A bit-field declared as `int' forces `int' alignment for the struct.  */
#define PCC_BITFIELD_TYPE_MATTERS 1

/* Make strings word-aligned so strcpy from constants will be faster.  */
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
  (TREE_CODE (EXP) == STRING_CST	\
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))

/* Make arrays of chars word-aligned for the same reasons.  */
#define DATA_ALIGNMENT(TYPE, ALIGN)		\
  (TREE_CODE (TYPE) == ARRAY_TYPE		\
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))

/* Set this nonzero if move instructions will actually fail to work
   when given unaligned data.  */
#define STRICT_ALIGNMENT 1

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.

   ROMP has 16 fullword registers and 8 floating point registers.

   In addition, the difference between the frame and argument pointers is
   a function of the number of registers saved, so we need to have a register
   to use for AP that will later be eliminated in favor of sp or fp.  This is
   a normal register, but it is fixed.  */

#define FIRST_PSEUDO_REGISTER 25

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.

   On ROMP, r1 is used for the stack and r14 is used for a
   data area pointer.

   HACK WARNING:  On the RT, there is a bug in code generation for
   the MC68881 when the first and third operands are the same floating-point
   register.  See the definition of the FINAL_PRESCAN_INSN macro for details.
   Here we need to reserve fr0 for this purpose.  */
#define FIXED_REGISTERS  \
 {0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
  1,							\
  1, 0, 0, 0, 0, 0, 0, 0}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */
#define CALL_USED_REGISTERS				\
 {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
  1,							\
  1, 1, 0, 0, 0, 0, 0, 0}

/* List the order in which to allocate registers.  Each register must be
   listed once, even those in FIXED_REGISTERS.

   We allocate in the following order:
	fr0, fr1	(not saved)
	fr2 ... fr6
	fr7		(more expensive for some FPA's)
	r0		(not saved and won't conflict with parameter register)
	r4, r3, r2	(not saved, highest used first to make less conflict)
	r5		(not saved, but forces r6 to be saved if DI/DFmode)
	r15, r14, r13, r12, r11, r10, r9, r8, r7, r6 (less to save)
	r1, ap 			*/

#define REG_ALLOC_ORDER		\
  {17, 18,			\
   19, 20, 21, 22, 23,		\
   24,				\
   0,				\
   4, 3, 2,			\
   5,				\
   15, 14, 13, 12, 11, 10,	\
   9, 8, 7, 6, 			\
   1, 16}

/* True if register is floating-point.  */
#define FP_REGNO_P(N) ((N) >= 17)

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   On ROMP, ordinary registers hold 32 bits worth;
   a single floating point register is always enough for
   anything that can be stored in them at all.  */
#define HARD_REGNO_NREGS(REGNO, MODE)   \
  (FP_REGNO_P (REGNO) ? GET_MODE_NUNITS (MODE)	\
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   On ROMP, the cpu registers can hold any mode but the float registers
   can hold only floating point.  */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
  (! FP_REGNO_P (REGNO) || GET_MODE_CLASS (MODE) == MODE_FLOAT	\
   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2) \
  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT		\
    || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT		\
       || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))

/* A C expression returning the cost of moving data from a register of class
   CLASS1 to one of CLASS2.

   On the ROMP, access to floating-point registers is expensive (even between
   two FP regs.)  */
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)	\
  (2 + 10 * ((CLASS1) == FP_REGS) + 10 * (CLASS2 == FP_REGS))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* ROMP pc isn't overloaded on a register that the compiler knows about.  */
/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM 1

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM 13

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */
#define FRAME_POINTER_REQUIRED 0

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM 16

/* Place to put static chain when calling a function that requires it.  */
#define STATIC_CHAIN							\
  gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -36))

/* Place where static chain is found upon entry to routine.  */
#define STATIC_CHAIN_INCOMING						\
  gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -20))

/* Place that structure value return address is placed.

   On the ROMP, it is passed as an extra parameter.  */
#define STRUCT_VALUE	0

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */
   
/* The ROMP has two types of registers, general and floating-point.

   However, r0 is special in that it cannot be used as a base register.
   So make a class for registers valid as base registers.

   For floating-point support, add classes that just consist of r0 and
   r15, respectively.  */

enum reg_class { NO_REGS, R0_REGS, R15_REGS, BASE_REGS, GENERAL_REGS,
		 FP_REGS, ALL_REGS, LIM_REG_CLASSES };

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.   */

#define REG_CLASS_NAMES \
 {"NO_REGS", "R0_REGS", "R15_REGS", "BASE_REGS", "GENERAL_REGS", \
  "FP_REGS", "ALL_REGS" }

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS {{0}, {0x00001}, {0x08000}, {0x1fffe}, {0x1ffff},  \
			    {0x1fe0000}, {0x1ffffff} }

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

#define REGNO_REG_CLASS(REGNO) \
 ((REGNO) == 0 ? GENERAL_REGS : FP_REGNO_P (REGNO) ? FP_REGS : BASE_REGS)

/* The class value for index registers, and the one for base regs.  */
#define INDEX_REG_CLASS BASE_REGS
#define BASE_REG_CLASS BASE_REGS

/* Get reg_class from a letter such as appears in the machine description.  */

#define REG_CLASS_FROM_LETTER(C) \
  ((C) == 'f' ? FP_REGS		\
   : (C) == 'b' ? BASE_REGS	\
   : (C) == 'z' ? R0_REGS	\
   : (C) == 't' ? R15_REGS	\
   : NO_REGS)

/* The letters I, J, K, L, M, N, and P in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.

   `I' is constants less than 16
   `J' is negative constants greater than -16
   `K' is the range for a normal D insn.
   `L' is a constant with only the low-order 16 bits set
   `M' is a constant with only the high-order 16 bits set
   `N' is a single-bit constant
   `O' is a constant with either the high-order or low-order 16 bits all ones
   `P' is the complement of a single-bit constant
  */

#define CONST_OK_FOR_LETTER_P(VALUE, C)  		   \
   ( (C) == 'I' ? (unsigned) (VALUE) < 0x10		   \
   : (C) == 'J' ? (VALUE) < 0 && (VALUE) > -16		   \
   : (C) == 'K' ? (unsigned) ((VALUE) + 0x8000) < 0x10000  \
   : (C) == 'L' ? ((VALUE) & 0xffff0000) == 0		   \
   : (C) == 'M' ? ((VALUE) & 0xffff) == 0		   \
   : (C) == 'N' ? exact_log2 (VALUE) >= 0		   \
   : (C) == 'O' ? ((VALUE) & 0xffff) == 0xffff		   \
		  || ((VALUE) & 0xffff0000) == 0xffff0000  \
   : (C) == 'P' ? exact_log2 (~ (VALUE)) >= 0		   \
   : 0)

/* Similar, but for floating constants, and defining letters G and H.
   Here VALUE is the CONST_DOUBLE rtx itself.