arc.md

linux下的gcc编译器

   sexw%? %0,%1
   ldw.x%U1 %0,%1"
  [(set_attr "type" "unary,load")])

(define_insn "*extendhisi2_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI (match_dup 1)))]
  ""
  "sexw%?.f %0,%1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set_zn")])

;; Arithmetic instructions.

(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_operand:SI 1 "register_operand" "%r")
		 (match_operand:SI 2 "nonmemory_operand" "rIJ")))]
  ""
  "add%? %0,%1,%2")

(define_insn "*addsi3_set_cc_insn"
  [(set (reg:CC 61) (compare:CC
		     (plus:SI (match_operand:SI 1 "register_operand" "%r")
			      (match_operand:SI 2 "nonmemory_operand" "rIJ"))
		     (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_dup 1)
		 (match_dup 2)))]
  ""
  "add%?.f %0,%1,%2"
  [(set_attr "cond" "set")])

(define_insn "adddi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (match_operand:DI 1 "nonmemory_operand" "%r")
		 (match_operand:DI 2 "nonmemory_operand" "ri")))
   (clobber (reg:CC 61))]
  ""
  "*
{
  rtx op2 = operands[2];

  if (GET_CODE (op2) == CONST_INT)
    {
      int sign = INTVAL (op2);
      if (sign < 0)
	return \"add.f %L0,%L1,%2\;adc %H0,%H1,-1\";
      else
	return \"add.f %L0,%L1,%2\;adc %H0,%H1,0\";
    }
  else
    return \"add.f %L0,%L1,%L2\;adc %H0,%H1,%H2\";
}"
  [(set_attr "length" "2")])

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "r")
		  (match_operand:SI 2 "nonmemory_operand" "rIJ")))]
  ""
  "sub%? %0,%1,%2")

(define_insn "*subsi3_set_cc_insn"
  [(set (reg:CC 61) (compare:CC
		     (minus:SI (match_operand:SI 1 "register_operand" "%r")
			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
		     (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_dup 1)
		  (match_dup 2)))]
  ""
  "sub%?.f %0,%1,%2"
  [(set_attr "cond" "set")])

(define_insn "subdi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(minus:DI (match_operand:DI 1 "nonmemory_operand" "r")
		  (match_operand:DI 2 "nonmemory_operand" "ri")))
   (clobber (reg:CC 61))]
  ""
  "*
{
  rtx op2 = operands[2];

  if (GET_CODE (op2) == CONST_INT)
    {
      int sign = INTVAL (op2);
      if (sign < 0)
	return \"sub.f %L0,%L1,%2\;sbc %H0,%H1,-1\";
      else
	return \"sub.f %L0,%L1,%2\;sbc %H0,%H1,0\";
    }
  else
    return \"sub.f %L0,%L1,%L2\;sbc %H0,%H1,%H2\";
}"
  [(set_attr "length" "2")])

;; Boolean instructions.
;;
;; We don't define the DImode versions as expand_binop does a good enough job.

(define_insn "andsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "nonmemory_operand" "rIJ")))]
  ""
  "and%? %0,%1,%2")

(define_insn "*andsi3_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (and:SI (match_operand:SI 1 "register_operand" "%r")
			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_dup 1)
		(match_dup 2)))]
  ""
  "and%?.f %0,%1,%2"
  [(set_attr "cond" "set_zn")])

(define_insn "*bicsi3_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(and:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
		(not:SI (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r"))))]
  ""
  "bic%? %0,%1,%2"
  [(set_attr "length" "1,2,1,2")])

(define_insn "*bicsi3_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (and:SI (match_operand:SI 1 "register_operand" "%r")
			       (not:SI (match_operand:SI 2 "nonmemory_operand" "rIJ")))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_dup 1)
		(not:SI (match_dup 2))))]
  ""
  "bic%?.f %0,%1,%2"
  [(set_attr "cond" "set_zn")])

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "nonmemory_operand" "rIJ")))]
  ""
  "or%? %0,%1,%2")

(define_insn "*iorsi3_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (ior:SI (match_operand:SI 1 "register_operand" "%r")
			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_dup 1)
		(match_dup 2)))]
  ""
  "or%?.f %0,%1,%2"
  [(set_attr "cond" "set_zn")])

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(xor:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "nonmemory_operand" "rIJ")))]
  ""
  "xor%? %0,%1,%2")

(define_insn "*xorsi3_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (xor:SI (match_operand:SI 1 "register_operand" "%r")
			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(xor:SI (match_dup 1)
		(match_dup 2)))]
  ""
  "xor%?.f %0,%1,%2"
  [(set_attr "cond" "set_zn")])

(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
  ""
  "sub%? %0,0,%1"
  [(set_attr "type" "unary")])

(define_insn "*negsi2_set_cc_insn"
  [(set (reg:CC 61) (compare:CC
		     (neg:SI (match_operand:SI 1 "register_operand" "r"))
		     (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_dup 1)))]
  ""
  "sub%?.f %0,0,%1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set")])

(define_insn "negdi2"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(neg:DI (match_operand:DI 1 "register_operand" "r")))
   (clobber (reg:SI 61))]
  ""
  "sub.f %L0,0,%L1\;sbc %H0,0,%H1"
  [(set_attr "type" "unary")
   (set_attr "length" "2")])

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(not:SI (match_operand:SI 1 "register_operand" "r")))]
  ""
  "xor%? %0,%1,-1"
  [(set_attr "type" "unary")])

(define_insn "*one_cmplsi2_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (not:SI (match_operand:SI 1 "register_operand" "r"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(not:SI (match_dup 1)))]
  ""
  "xor%?.f %0,%1,-1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set_zn")])

;; Shift instructions.

(define_expand "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ashift:SI (match_operand:SI 1 "register_operand" "")
		   (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (! TARGET_SHIFTER)
    {
      emit_insn (gen_rtx_PARALLEL
		 (VOIDmode,
		  gen_rtvec (2,
			     gen_rtx_SET (VOIDmode, operands[0],
					  gen_rtx_ASHIFT (SImode, operands[1],
							  operands[2])),
			     gen_rtx_CLOBBER (VOIDmode,
					      gen_rtx_SCRATCH (SImode)))));
      DONE;
    }
}")

(define_expand "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
		     (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (! TARGET_SHIFTER)
    {
      emit_insn (gen_rtx_PARALLEL
		 (VOIDmode,
		  gen_rtvec (2,
			     gen_rtx_SET (VOIDmode, operands[0],
					  gen_rtx_ASHIFTRT (SImode,
							    operands[1],
							    operands[2])),
			     gen_rtx_CLOBBER (VOIDmode,
					      gen_rtx_SCRATCH (SImode)))));
      DONE;
    }
}")

(define_expand "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
		     (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (! TARGET_SHIFTER)
    {
      emit_insn (gen_rtx_PARALLEL
		 (VOIDmode,
		  gen_rtvec (2,
			     gen_rtx_SET (VOIDmode, operands[0],
					  gen_rtx_LSHIFTRT (SImode,
							    operands[1],
							    operands[2])),
			     gen_rtx_CLOBBER (VOIDmode,
					      gen_rtx_SCRATCH (SImode)))));
      DONE;
    }
}")

(define_insn "*ashlsi3_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(ashift:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
		   (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r")))]
  "TARGET_SHIFTER"
  "asl%? %0,%1,%2"
  [(set_attr "type" "shift")
   (set_attr "length" "1,2,1,2")])

(define_insn "*ashrsi3_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
		     (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r")))]
  "TARGET_SHIFTER"
  "asr%? %0,%1,%2"
  [(set_attr "type" "shift")
   (set_attr "length" "1,2,1,2")])

(define_insn "*lshrsi3_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(lshiftrt:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
		     (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r")))]
  "TARGET_SHIFTER"
  "lsr%? %0,%1,%2"
  [(set_attr "type" "shift")
   (set_attr "length" "1,2,1,2")])

(define_insn "*shift_si3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operator:SI 3 "shift_operator"
			   [(match_operand:SI 1 "register_operand" "0")
			    (match_operand:SI 2 "nonmemory_operand" "rIJ")]))
   (clobber (match_scratch:SI 4 "=&r"))]
  "! TARGET_SHIFTER"
  "* return output_shift (operands);"
  [(set_attr "type" "shift")
   (set_attr "length" "8")])

;; Compare instructions.
;; This controls RTL generation and register allocation.

;; We generate RTL for comparisons and branches by having the cmpxx 
;; patterns store away the operands.  Then, the scc and bcc patterns
;; emit RTL for both the compare and the branch.

(define_expand "cmpsi"
  [(set (reg:CC 61)
	(compare:CC (match_operand:SI 0 "register_operand" "")
		    (match_operand:SI 1 "nonmemory_operand" "")))]
  ""
  "
{
  arc_compare_op0 = operands[0];
  arc_compare_op1 = operands[1];
  DONE;
}")

;; ??? We may be able to relax this a bit by adding a new constant 'K' for 0.
;; This assumes sub.f 0,symbol,0 is a valid insn.
;; Note that "sub.f 0,r0,1" is an 8 byte insn.  To avoid unnecessarily
;; creating 8 byte insns we duplicate %1 in the destination reg of the insn
;; if it's a small constant.

(define_insn "*cmpsi_cc_insn"
  [(set (reg:CC 61)
	(compare:CC (match_operand:SI 0 "register_operand" "r,r,r")
		    (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
  ""
  "@
   sub.f 0,%0,%1
   sub.f %1,%0,%1
   sub.f 0,%0,%1"
  [(set_attr "type" "compare,compare,compare")])

(define_insn "*cmpsi_cczn_insn"
  [(set (reg:CCZN 61)
	(compare:CCZN (match_operand:SI 0 "register_operand" "r,r,r")
		      (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
  ""
  "@
   sub.f 0,%0,%1
   sub.f %1,%0,%1
   sub.f 0,%0,%1"
  [(set_attr "type" "compare,compare,compare")])

(define_insn "*cmpsi_ccznc_insn"
  [(set (reg:CCZNC 61)
	(compare:CCZNC (match_operand:SI 0 "register_operand" "r,r,r")
		       (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
  ""
  "@
   sub.f 0,%0,%1
   sub.f %1,%0,%1
   sub.f 0,%0,%1"
  [(set_attr "type" "compare,compare,compare")])

;; Next come the scc insns.

(define_expand "seq"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = gen_compare_reg (EQ, arc_compare_op0, arc_compare_op1);
}")

(define_expand "sne"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = gen_compare_reg (NE, arc_compare_op0, arc_compare_op1);