arc.md

linux下的gcc编译器

;  DONE;
;}")

;; Load/Store with update instructions.
;;
;; Some of these we can get by using pre-decrement or pre-increment, but the
;; hardware can also do cases where the increment is not the size of the
;; object.
;;
;; In all these cases, we use operands 0 and 1 for the register being
;; incremented because those are the operands that local-alloc will
;; tie and these are the pair most likely to be tieable (and the ones
;; that will benefit the most).
;;
;; We use match_operator here because we need to know whether the memory
;; object is volatile or not.

(define_insn "*loadqi_update"
  [(set (match_operand:QI 3 "register_operand" "=r,r")
	(match_operator:QI 4 "load_update_operand"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ldb.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*load_zeroextendqisi_update"
  [(set (match_operand:SI 3 "register_operand" "=r,r")
	(zero_extend:SI (match_operator:QI 4 "load_update_operand"
			 [(match_operand:SI 1 "register_operand" "0,0")
			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ldb.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*load_signextendqisi_update"
  [(set (match_operand:SI 3 "register_operand" "=r,r")
	(sign_extend:SI (match_operator:QI 4 "load_update_operand"
			 [(match_operand:SI 1 "register_operand" "0,0")
			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ldb.x.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*storeqi_update"
  [(set (match_operator:QI 4 "store_update_operand"
	 [(match_operand:SI 1 "register_operand" "0")
	  (match_operand:SI 2 "short_immediate_operand" "I")])
	(match_operand:QI 3 "register_operand" "r"))
   (set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "stb.a%V4 %3,[%0,%2]"
  [(set_attr "type" "store")
   (set_attr "length" "1")])

(define_insn "*loadhi_update"
  [(set (match_operand:HI 3 "register_operand" "=r,r")
	(match_operator:HI 4 "load_update_operand"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ldw.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*load_zeroextendhisi_update"
  [(set (match_operand:SI 3 "register_operand" "=r,r")
	(zero_extend:SI (match_operator:HI 4 "load_update_operand"
			 [(match_operand:SI 1 "register_operand" "0,0")
			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ldw.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*load_signextendhisi_update"
  [(set (match_operand:SI 3 "register_operand" "=r,r")
	(sign_extend:SI (match_operator:HI 4 "load_update_operand"
			 [(match_operand:SI 1 "register_operand" "0,0")
			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ldw.x.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*storehi_update"
  [(set (match_operator:HI 4 "store_update_operand"
	 [(match_operand:SI 1 "register_operand" "0")
	  (match_operand:SI 2 "short_immediate_operand" "I")])
	(match_operand:HI 3 "register_operand" "r"))
   (set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "stw.a%V4 %3,[%0,%2]"
  [(set_attr "type" "store")
   (set_attr "length" "1")])

(define_insn "*loadsi_update"
  [(set (match_operand:SI 3 "register_operand" "=r,r")
	(match_operator:SI 4 "load_update_operand"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ld.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*storesi_update"
  [(set (match_operator:SI 4 "store_update_operand"
	 [(match_operand:SI 1 "register_operand" "0")
	  (match_operand:SI 2 "short_immediate_operand" "I")])
	(match_operand:SI 3 "register_operand" "r"))
   (set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "st.a%V4 %3,[%0,%2]"
  [(set_attr "type" "store")
   (set_attr "length" "1")])

(define_insn "*loadsf_update"
  [(set (match_operand:SF 3 "register_operand" "=r,r")
	(match_operator:SF 4 "load_update_operand"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
   (set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "ld.a%V4 %3,[%0,%2]"
  [(set_attr "type" "load,load")
   (set_attr "length" "1,2")])

(define_insn "*storesf_update"
  [(set (match_operator:SF 4 "store_update_operand"
	 [(match_operand:SI 1 "register_operand" "0")
	  (match_operand:SI 2 "short_immediate_operand" "I")])
	(match_operand:SF 3 "register_operand" "r"))
   (set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_dup 1) (match_dup 2)))]
  ""
  "st.a%V4 %3,[%0,%2]"
  [(set_attr "type" "store")
   (set_attr "length" "1")])

;; Conditional move instructions.

(define_expand "movsicc"
  [(set (match_operand:SI 0 "register_operand" "")
	(if_then_else:SI (match_operand 1 "comparison_operator" "")
			 (match_operand:SI 2 "nonmemory_operand" "")
			 (match_operand:SI 3 "register_operand" "")))]
  ""
  "
{
  enum rtx_code code = GET_CODE (operands[1]);
  rtx ccreg
    = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
		   61);

  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
}")

;(define_expand "movdicc"
;  [(set (match_operand:DI 0 "register_operand" "")
;	(if_then_else:DI (match_operand 1 "comparison_operator" "")
;			 (match_operand:DI 2 "nonmemory_operand" "")
;			 (match_operand:DI 3 "register_operand" "")))]
;  "0 /* ??? this would work better if we had cmpdi */"
;  "
;{
;  enum rtx_code code = GET_CODE (operands[1]);
;  rtx ccreg
;   = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
;		   61);
;
;  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
;}")

(define_expand "movsfcc"
  [(set (match_operand:SF 0 "register_operand" "")
	(if_then_else:SF (match_operand 1 "comparison_operator" "")
			 (match_operand:SF 2 "nonmemory_operand" "")
			 (match_operand:SF 3 "register_operand" "")))]
  ""
  "
{
  enum rtx_code code = GET_CODE (operands[1]);
  rtx ccreg
    = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
		   61);

  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
}")

;(define_expand "movdfcc"
;  [(set (match_operand:DF 0 "register_operand" "")
;	(if_then_else:DF (match_operand 1 "comparison_operator" "")
;			 (match_operand:DF 2 "nonmemory_operand" "")
;			 (match_operand:DF 3 "register_operand" "")))]
;  "0 /* ??? can generate less efficient code if constants involved */"
;  "
;{
; enum rtx_code code = GET_CODE (operands[1]);
; rtx ccreg
;   = gen_rtx_REG (SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
;		   61);
;
;  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
;}")

(define_insn "*movsicc_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(if_then_else:SI (match_operand 1 "comparison_operator" "")
			 (match_operand:SI 2 "nonmemory_operand" "rJi")
			 (match_operand:SI 3 "register_operand" "0")))]
  ""
  "mov.%d1 %0,%S2"
  [(set_attr "type" "cmove")])

; ??? This doesn't properly handle constants.
;(define_insn "*movdicc_insn"
;  [(set (match_operand:DI 0 "register_operand" "=r,r")
;	(if_then_else:DI (match_operand 1 "comparison_operator" "")
;			 (match_operand:DI 2 "nonmemory_operand" "r,Ji")
;			 (match_operand:DI 3 "register_operand" "0,0")))]
;  "0"
;  "*
;{
;  switch (which_alternative)
;    {
;    case 0 :
;      /* We normally copy the low-numbered register first.  However, if
;	 the first register operand 0 is the same as the second register of
;	 operand 1, we must copy in the opposite order.  */
;      if (REGNO (operands[0]) == REGNO (operands[2]) + 1)
;	return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\";
;      else
;	return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
;    case 1 :
;      return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
;    }
;}"
;  [(set_attr "type" "cmove,cmove")
;   (set_attr "length" "2,4")])

(define_insn "*movsfcc_insn"
  [(set (match_operand:SF 0 "register_operand" "=r,r")
	(if_then_else:SF (match_operand 1 "comparison_operator" "")
			 (match_operand:SF 2 "nonmemory_operand" "r,E")
			 (match_operand:SF 3 "register_operand" "0,0")))]
  ""
  "@
   mov.%d1 %0,%2
   mov.%d1 %0,%2 ; %A2"
  [(set_attr "type" "cmove,cmove")])

;(define_insn "*movdfcc_insn"
;  [(set (match_operand:DF 0 "register_operand" "=r,r")
;	(if_then_else:DF (match_operand 1 "comparison_operator" "")
;			 (match_operand:DF 2 "nonmemory_operand" "r,E")
;			 (match_operand:DF 3 "register_operand" "0,0")))]
;  "0"
;  "*
;{
;  switch (which_alternative)
;    {
;    case 0 :
;      /* We normally copy the low-numbered register first.  However, if
;	 the first register operand 0 is the same as the second register of
;	 operand 1, we must copy in the opposite order.  */
;      if (REGNO (operands[0]) == REGNO (operands[2]) + 1)
;	return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\";
;      else
;	return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
;    case 1 :
;      return \"mov.%d1 %0,%L2\;mov.%d1 %R0,%H2 ; %A2\";
;    }
;}"
;  [(set_attr "type" "cmove,cmove")
;   (set_attr "length" "2,4")])

;; Zero extension instructions.
;; ??? We don't support volatile memrefs here, but I'm not sure why.

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
  ""
  "@
   extb%? %0,%1
   ldb%U1 %0,%1"
  [(set_attr "type" "unary,load")])

(define_insn "*zero_extendqihi2_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
		       (const_int 0)))
   (set (match_operand:HI 0 "register_operand" "=r")
	(zero_extend:HI (match_dup 1)))]
  ""
  "extb%?.f %0,%1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set_zn")])

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
  ""
  "@
   extb%? %0,%1
   ldb%U1 %0,%1"
  [(set_attr "type" "unary,load")])

(define_insn "*zero_extendqisi2_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_dup 1)))]
  ""
  "extb%?.f %0,%1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set_zn")])

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "r,m")))]
  ""
  "@
   extw%? %0,%1
   ldw%U1 %0,%1"
  [(set_attr "type" "unary,load")])

(define_insn "*zero_extendhisi2_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_dup 1)))]
  ""
  "extw%?.f %0,%1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set_zn")])

;; Sign extension instructions.

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
  ""
  "@
   sexb%? %0,%1
   ldb.x%U1 %0,%1"
  [(set_attr "type" "unary,load")])

(define_insn "*extendqihi2_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (sign_extend:SI (match_operand:QI 1 "register_operand" "r"))
		       (const_int 0)))
   (set (match_operand:HI 0 "register_operand" "=r")
	(sign_extend:HI (match_dup 1)))]
  ""
  "sexb%?.f %0,%1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set_zn")])

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
  ""
  "@
   sexb%? %0,%1
   ldb.x%U1 %0,%1"
  [(set_attr "type" "unary,load")])

(define_insn "*extendqisi2_set_cc_insn"
  [(set (reg:CCZN 61) (compare:CCZN
		       (sign_extend:SI (match_operand:QI 1 "register_operand" "r"))
		       (const_int 0)))
   (set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI (match_dup 1)))]
  ""
  "sexb%?.f %0,%1"
  [(set_attr "type" "unary")
   (set_attr "cond" "set_zn")])

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "r,m")))]
  ""
  "@