pa.h

linux下的gcc编译器

	    fputs ("\t.word	0\n", FILE);				\
	  }								\
	else								\
	  {								\
	    fputs ("\tldsid	(%r21),%r1\n", FILE);			\
	    fputs ("\tmtsp	%r1,%sr0\n", FILE);			\
	    fputs ("\tbe	0(%sr0,%r21)\n", FILE);			\
	    fputs ("\tldw	40(%r22),%r29\n", FILE);		\
	  }								\
	fputs ("\t.word	0\n", FILE);					\
	fputs ("\t.word	0\n", FILE);					\
	fputs ("\t.word	0\n", FILE);					\
	fputs ("\t.word	0\n", FILE);					\
      }									\
    else								\
      {									\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\tmfia	%r31\n", FILE);					\
	fputs ("\tldd	24(%r31),%r1\n", FILE);				\
	fputs ("\tldd	24(%r1),%r27\n", FILE);				\
	fputs ("\tldd	16(%r1),%r1\n", FILE);				\
	fputs ("\tbve	(%r1)\n", FILE);				\
	fputs ("\tldd	32(%r31),%r31\n", FILE);			\
	fputs ("\t.dword 0  ; fptr\n", FILE);				\
	fputs ("\t.dword 0  ; static link\n", FILE);			\
      }									\
  }

/* Length in units of the trampoline for entering a nested function.  */

#define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)

/* Length in units of the trampoline instruction code.  */

#define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))

/* Minimum length of a cache line.  A length of 16 will work on all
   PA-RISC processors.  All PA 1.1 processors have a cache line of
   32 bytes.  Most but not all PA 2.0 processors have a cache line
   of 64 bytes.  As cache flushes are expensive and we don't support
   PA 1.0, we use a minimum length of 32.  */

#define MIN_CACHELINE_SIZE 32

/* Emit RTL insns to initialize the variable parts of a trampoline.
   FNADDR is an RTX for the address of the function's pure code.
   CXT is an RTX for the static chain value for the function.

   Move the function address to the trampoline template at offset 36.
   Move the static chain value to trampoline template at offset 40.
   Move the trampoline address to trampoline template at offset 44.
   Move r19 to trampoline template at offset 48.  The latter two
   words create a plabel for the indirect call to the trampoline.

   A similar sequence is used for the 64-bit port but the plabel is
   at the beginning of the trampoline.

   Finally, the cache entries for the trampoline code are flushed.
   This is necessary to ensure that the trampoline instruction sequence
   is written to memory prior to any attempts at prefetching the code
   sequence.  */

#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) 			\
{									\
  rtx start_addr = gen_reg_rtx (Pmode);					\
  rtx end_addr = gen_reg_rtx (Pmode);					\
  rtx line_length = gen_reg_rtx (Pmode);				\
  rtx tmp;								\
									\
  if (!TARGET_64BIT)							\
    {									\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 36));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR));		\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 40));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT));			\
									\
      /* Create a fat pointer for the trampoline.  */			\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 44));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP));		\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 48));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp),				\
		      gen_rtx_REG (Pmode, 19));				\
									\
      /* fdc and fic only use registers for the address to flush,	\
	 they do not accept integer displacements.  We align the	\
	 start and end addresses to the beginning of their respective	\
	 cache lines to minimize the number of lines flushed.  */	\
      tmp = force_reg (Pmode, (TRAMP));					\
      emit_insn (gen_andsi3 (start_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      tmp = force_reg (Pmode,						\
		       plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));	\
      emit_insn (gen_andsi3 (end_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));	\
      emit_insn (gen_dcacheflush (start_addr, end_addr, line_length));	\
      emit_insn (gen_icacheflush (start_addr, end_addr, line_length,	\
				  gen_reg_rtx (Pmode),			\
				  gen_reg_rtx (Pmode)));		\
    }									\
  else									\
    {									\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 56));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR));		\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 64));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT));			\
									\
      /* Create a fat pointer for the trampoline.  */			\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 16));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp),				\
		      force_reg (Pmode, plus_constant ((TRAMP), 32)));	\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 24));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp),				\
		      gen_rtx_REG (Pmode, 27));				\
									\
      /* fdc and fic only use registers for the address to flush,	\
	 they do not accept integer displacements.  We align the	\
	 start and end addresses to the beginning of their respective	\
	 cache lines to minimize the number of lines flushed.  */	\
      tmp = force_reg (Pmode, plus_constant ((TRAMP), 32));		\
      emit_insn (gen_anddi3 (start_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      tmp = force_reg (Pmode,						\
		       plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));	\
      emit_insn (gen_anddi3 (end_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));	\
      emit_insn (gen_dcacheflush (start_addr, end_addr, line_length));	\
      emit_insn (gen_icacheflush (start_addr, end_addr, line_length,	\
				  gen_reg_rtx (Pmode),			\
				  gen_reg_rtx (Pmode)));		\
    }									\
}

/* Perform any machine-specific adjustment in the address of the trampoline.
   ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
   Adjust the trampoline address to point to the plabel at offset 44.  */
   
#define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
  if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))

/* Emit code for a call to builtin_saveregs.  We must emit USE insns which
   reference the 4 integer arg registers and 4 fp arg registers.
   Ordinarily they are not call used registers, but they are for
   _builtin_saveregs, so we must make this explicit.  */

#define EXPAND_BUILTIN_SAVEREGS() hppa_builtin_saveregs ()

/* Implement `va_start' for varargs and stdarg.  */

#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
  hppa_va_start (valist, nextarg)

/* Implement `va_arg'.  */

#define EXPAND_BUILTIN_VA_ARG(valist, type) \
  hppa_va_arg (valist, type)

/* Addressing modes, and classification of registers for them. 

   Using autoincrement addressing modes on PA8000 class machines is
   not profitable.  */

#define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)

#define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)

/* Macros to check register numbers against specific register classes.  */

/* These assume that REGNO is a hard or pseudo reg number.
   They give nonzero only if REGNO is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   Since they use reg_renumber, they are safe only once reg_renumber
   has been allocated, which happens in local-alloc.c.  */

#define REGNO_OK_FOR_INDEX_P(REGNO) \
  ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
#define REGNO_OK_FOR_BASE_P(REGNO)  \
  ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
#define REGNO_OK_FOR_FP_P(REGNO) \
  (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))

/* Now macros that check whether X is a register and also,
   strictly, whether it is in a specified class.

   These macros are specific to the HP-PA, and may be used only
   in code for printing assembler insns and in conditions for
   define_optimization.  */

/* 1 if X is an fp register.  */

#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))

/* Maximum number of registers that can appear in a valid memory address.  */

#define MAX_REGS_PER_ADDRESS 2

/* Recognize any constant value that is a valid address except
   for symbolic addresses.  We get better CSE by rejecting them
   here and allowing hppa_legitimize_address to break them up.  We
   use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE.  */

#define CONSTANT_ADDRESS_P(X) \
  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
   || GET_CODE (X) == HIGH) 						\
   && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))

/* Include all constant integers and constant doubles, but not
   floating-point, except for floating-point zero.

   Reject LABEL_REFs if we're not using gas or the new HP assembler. 

   ?!? For now also reject CONST_DOUBLES in 64bit mode.  This will need
   further work.  */
#ifndef NEW_HP_ASSEMBLER
#define NEW_HP_ASSEMBLER 0
#endif
#define LEGITIMATE_CONSTANT_P(X)				\
  ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT			\
    || (X) == CONST0_RTX (GET_MODE (X)))			\
   && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF)	\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE)		\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_INT		\
	&& !(HOST_BITS_PER_WIDE_INT <= 32			\
	     || (INTVAL (X) >= (HOST_WIDE_INT) -32 << 31	\
		 && INTVAL (X) < (HOST_WIDE_INT) 32 << 31)	\
	     || cint_ok_for_move (INTVAL (X))))			\
   && !function_label_operand (X, VOIDmode))

/* Subroutine for EXTRA_CONSTRAINT.

   Return 1 iff OP is a pseudo which did not get a hard register and
   we are running the reload pass.  */

#define IS_RELOADING_PSEUDO_P(OP) \
  ((reload_in_progress					\
    && GET_CODE (OP) == REG				\
    && REGNO (OP) >= FIRST_PSEUDO_REGISTER		\
    && reg_renumber [REGNO (OP)] < 0))

/* Optional extra constraints for this machine. Borrowed from sparc.h.

   For the HPPA, `Q' means that this is a memory operand but not a
   symbolic memory operand.  Note that an unassigned pseudo register
   is such a memory operand.  Needed because reload will generate
   these things in insns and then not re-recognize the insns, causing
   constrain_operands to fail.

   `R' is used for scaled indexed addresses.

   `S' is the constant 31.

   `T' is for floating-point loads and stores.  */
#define EXTRA_CONSTRAINT(OP, C)				\
  ((C) == 'Q' ?						\
   (IS_RELOADING_PSEUDO_P (OP)				\
    || (GET_CODE (OP) == MEM				\
	&& (memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
	    || reload_in_progress)			\
	&& ! symbolic_memory_operand (OP, VOIDmode)	\
        && !(GET_CODE (XEXP (OP, 0)) == PLUS		\
	     && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
		 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))))\
   : ((C) == 'R' ?					\
     (GET_CODE (OP) == MEM				\
      && GET_CODE (XEXP (OP, 0)) == PLUS		\
      && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT	\
	  || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)	\
      && (move_operand (OP, GET_MODE (OP))		\
	  || memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
	  || reload_in_progress))			\
   : ((C) == 'T' ?							\
      (GET_CODE (OP) == MEM						\
       /* Floating-point loads and stores are used to load		\
	  integer values as well as floating-point values.		\
	  They don't have the same set of REG+D address modes		\
	  as integer loads and stores.  PA 1.x supports only		\
	  short displacements.  PA 2.0 supports long displacements	\
	  but the base register needs to be aligned.			\
									\
	  The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and		\
	  DFmode test the validity of an address for use in a           \
	  floating point load or store.  So, we use SFmode/DFmode       \
	  to see if the address is valid for a floating-point           \
	  load/store operation.  */                                     \
       && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4		\
			     ? SFmode					\
			     : DFmode),					\
			    XEXP (OP, 0))				\
       && !(GET_CODE (XEXP (OP, 0)) == LO_SUM		\
	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
	    && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0))\
	    && GET_CODE (XEXP (XEXP (OP, 0), 1)) == UNSPEC\
	    && GET_MODE (XEXP (OP, 0)) == Pmode)	\
       && !(GET_CODE (XEXP (OP, 0)) == PLUS		\
	    && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
		|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)))\
   : ((C) == 'U' ?					\
      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63)	\
   : ((C) == 'A' ?					\
      (GET_CODE (OP) == MEM				\
       && GET_CODE (XEXP (OP, 0)) == LO_SUM		\
       && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG	\
       && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0))	\
       && GET_CODE (XEXP (XEXP (OP, 0), 1)) == UNSPEC		\
       && GET_MODE (XEXP (OP, 0)) == Pmode)			\
   : ((C) == 'S' ?					\
      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) : 0))))))
	

/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
   and check its validity for a certain class.
   We have two alternate definitions for each of them.
   The usual definition accepts all pseudo regs; the other rejects
   them unless they have been allocated suitable hard regs.
   The symbol REG_OK_STRICT causes the latter definition to be used.

   Most source files want to accept pseudo regs in the hope that
   they will get allocated to the class that the insn wants them to be in.
   Source files for reload pass need to be strict.
   After reload, it makes no difference, since pseudo regs have
   been eliminated by then.  */

#ifndef REG_OK_STRICT

/* Nonzero if X is a hard reg that can be used as an index
   or if it is a pseudo reg.  */
#define REG_OK_FOR_INDEX_P(X) \
(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
/* Nonzero if X is a hard reg that can be used as a base reg