arm.md

linux下的gcc编译器

(define_insn "*thumb_mulsi3"
  [(set (match_operand:SI          0 "register_operand" "=&l,&l,&l")
	(mult:SI (match_operand:SI 1 "register_operand" "%l,*h,0")
		 (match_operand:SI 2 "register_operand" "l,l,l")))]
  "TARGET_THUMB"
  "*
  if (which_alternative < 2)
    return \"mov\\t%0, %1\;mul\\t%0, %0, %2\";
  else
    return \"mul\\t%0, %0, %2\";
  "
  [(set_attr "length" "4,4,2")
   (set_attr "type" "mult")]
)

(define_insn "*mulsi3_compare0"
  [(set (reg:CC_NOOV CC_REGNUM)
	(compare:CC_NOOV (mult:SI
			  (match_operand:SI 2 "s_register_operand" "r,r")
			  (match_operand:SI 1 "s_register_operand" "%?r,0"))
			 (const_int 0)))
   (set (match_operand:SI 0 "s_register_operand" "=&r,&r")
	(mult:SI (match_dup 2) (match_dup 1)))]
  "TARGET_ARM && !arm_arch_xscale"
  "mul%?s\\t%0, %2, %1"
  [(set_attr "conds" "set")
   (set_attr "type" "mult")]
)

(define_insn "*mulsi_compare0_scratch"
  [(set (reg:CC_NOOV CC_REGNUM)
	(compare:CC_NOOV (mult:SI
			  (match_operand:SI 2 "s_register_operand" "r,r")
			  (match_operand:SI 1 "s_register_operand" "%?r,0"))
			 (const_int 0)))
   (clobber (match_scratch:SI 0 "=&r,&r"))]
  "TARGET_ARM && !arm_arch_xscale"
  "mul%?s\\t%0, %2, %1"
  [(set_attr "conds" "set")
   (set_attr "type" "mult")]
)

;; Unnamed templates to match MLA instruction.

(define_insn "*mulsi3addsi"
  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
	(plus:SI
	  (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
		   (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
	  (match_operand:SI 3 "s_register_operand" "?r,r,0,0")))]
  "TARGET_ARM"
  "mla%?\\t%0, %2, %1, %3"
  [(set_attr "type" "mult")
   (set_attr "predicable" "yes")]
)

(define_insn "*mulsi3addsi_compare0"
  [(set (reg:CC_NOOV CC_REGNUM)
	(compare:CC_NOOV
	 (plus:SI (mult:SI
		   (match_operand:SI 2 "s_register_operand" "r,r,r,r")
		   (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
		  (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
	 (const_int 0)))
   (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
	(plus:SI (mult:SI (match_dup 2) (match_dup 1))
		 (match_dup 3)))]
  "TARGET_ARM && !arm_arch_xscale"
  "mla%?s\\t%0, %2, %1, %3"
  [(set_attr "conds" "set")
   (set_attr "type" "mult")]
)

(define_insn "*mulsi3addsi_compare0_scratch"
  [(set (reg:CC_NOOV CC_REGNUM)
	(compare:CC_NOOV
	 (plus:SI (mult:SI
		   (match_operand:SI 2 "s_register_operand" "r,r,r,r")
		   (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
		  (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
	 (const_int 0)))
   (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
  "TARGET_ARM && !arm_arch_xscale"
  "mla%?s\\t%0, %2, %1, %3"
  [(set_attr "conds" "set")
   (set_attr "type" "mult")]
)

;; Unnamed template to match long long multiply-accumlate (smlal)

(define_insn "*mulsidi3adddi"
  [(set (match_operand:DI 0 "s_register_operand" "=&r")
	(plus:DI
	 (mult:DI
	  (sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
	  (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
	 (match_operand:DI 1 "s_register_operand" "0")))]
  "TARGET_ARM && arm_fast_multiply"
  "smlal%?\\t%Q0, %R0, %3, %2"
  [(set_attr "type" "mult")
   (set_attr "predicable" "yes")]
)

(define_insn "mulsidi3"
  [(set (match_operand:DI 0 "s_register_operand" "=&r")
	(mult:DI
	 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
	 (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
  "TARGET_ARM && arm_fast_multiply"
  "smull%?\\t%Q0, %R0, %1, %2"
  [(set_attr "type" "mult")
   (set_attr "predicable" "yes")]
)

(define_insn "umulsidi3"
  [(set (match_operand:DI 0 "s_register_operand" "=&r")
	(mult:DI
	 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
	 (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
  "TARGET_ARM && arm_fast_multiply"
  "umull%?\\t%Q0, %R0, %1, %2"
  [(set_attr "type" "mult")
   (set_attr "predicable" "yes")]
)

;; Unnamed template to match long long unsigned multiply-accumlate (umlal)

(define_insn "*umulsidi3adddi"
  [(set (match_operand:DI 0 "s_register_operand" "=&r")
	(plus:DI
	 (mult:DI
	  (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
	  (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
	 (match_operand:DI 1 "s_register_operand" "0")))]
  "TARGET_ARM && arm_fast_multiply"
  "umlal%?\\t%Q0, %R0, %3, %2"
  [(set_attr "type" "mult")
   (set_attr "predicable" "yes")]
)

(define_insn "smulsi3_highpart"
  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
	(truncate:SI
	 (lshiftrt:DI
	  (mult:DI
	   (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r,0"))
	   (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
	  (const_int 32))))
   (clobber (match_scratch:SI 3 "=&r,&r"))]
  "TARGET_ARM && arm_fast_multiply"
  "smull%?\\t%3, %0, %2, %1"
  [(set_attr "type" "mult")
   (set_attr "predicable" "yes")]
)

(define_insn "umulsi3_highpart"
  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
	(truncate:SI
	 (lshiftrt:DI
	  (mult:DI
	   (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r,0"))
	   (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
	  (const_int 32))))
   (clobber (match_scratch:SI 3 "=&r,&r"))]
  "TARGET_ARM && arm_fast_multiply"
  "umull%?\\t%3, %0, %2, %1"
  [(set_attr "type" "mult")
   (set_attr "predicable" "yes")]
)

(define_insn "mulhisi3"
  [(set (match_operand:SI 0 "s_register_operand" "=r")
	(mult:SI (sign_extend:SI
		  (match_operand:HI 1 "s_register_operand" "%r"))
		 (sign_extend:SI
		  (match_operand:HI 2 "s_register_operand" "r"))))]
  "TARGET_ARM && arm_arch_xscale"
  "smulbb%?\\t%0, %1, %2"
  [(set_attr "type" "mult")]
)

(define_insn "*mulhisi3addsi"
  [(set (match_operand:SI 0 "s_register_operand" "=r")
	(plus:SI (match_operand:SI 1 "s_register_operand" "r")
		 (mult:SI (sign_extend:SI
			   (match_operand:HI 2 "s_register_operand" "%r"))
			  (sign_extend:SI
			   (match_operand:HI 3 "s_register_operand" "r")))))]
  "TARGET_ARM && arm_arch_xscale"
  "smlabb%?\\t%0, %2, %3, %1"
  [(set_attr "type" "mult")]
)

(define_insn "*mulhidi3adddi"
  [(set (match_operand:DI 0 "s_register_operand" "=r")
	(plus:DI
	  (match_operand:DI 1 "s_register_operand" "0")
	  (mult:DI (sign_extend:DI
	 	    (match_operand:HI 2 "s_register_operand" "%r"))
		   (sign_extend:DI
		    (match_operand:HI 3 "s_register_operand" "r")))))]
  "TARGET_ARM && arm_arch_xscale"
  "smlalbb%?\\t%Q0, %R0, %2, %3"
[(set_attr "type" "mult")])

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "s_register_operand" "=f")
	(mult:SF (match_operand:SF 1 "s_register_operand" "f")
		 (match_operand:SF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "fml%?s\\t%0, %1, %2"
  [(set_attr "type" "ffmul")
   (set_attr "predicable" "yes")]
)

(define_insn "muldf3"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF (match_operand:DF 1 "s_register_operand" "f")
		 (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

(define_insn "*muldf_esfdf_df"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF (float_extend:DF
		  (match_operand:SF 1 "s_register_operand" "f"))
		 (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

(define_insn "*muldf_df_esfdf"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF (match_operand:DF 1 "s_register_operand" "f")
		 (float_extend:DF
		  (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

(define_insn "*muldf_esfdf_esfdf"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF
	 (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))
	 (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

(define_insn "mulxf3"
  [(set (match_operand:XF 0 "s_register_operand" "=f")
	(mult:XF (match_operand:XF 1 "s_register_operand" "f")
		 (match_operand:XF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
  "muf%?e\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

;; Division insns

(define_insn "divsf3"
  [(set (match_operand:SF 0 "s_register_operand" "=f,f")
	(div:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G")
		(match_operand:SF 2 "fpu_rhs_operand" "fG,f")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "@
   fdv%?s\\t%0, %1, %2
   frd%?s\\t%0, %2, %1"
  [(set_attr "type" "fdivs")
   (set_attr "predicable" "yes")]
)

(define_insn "divdf3"
  [(set (match_operand:DF 0 "s_register_operand" "=f,f")
	(div:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
		(match_operand:DF 2 "fpu_rhs_operand" "fG,f")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "@
   dvf%?d\\t%0, %1, %2
   rdf%?d\\t%0, %2, %1"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*divdf_esfdf_df"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(div:DF (float_extend:DF
		 (match_operand:SF 1 "s_register_operand" "f"))
		(match_operand:DF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "dvf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*divdf_df_esfdf"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(div:DF (match_operand:DF 1 "fpu_rhs_operand" "fG")
		(float_extend:DF
		 (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "rdf%?d\\t%0, %2, %1"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*divdf_esfdf_esfdf"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(div:DF (float_extend:DF
		 (match_operand:SF 1 "s_register_operand" "f"))
		(float_extend:DF
		 (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "dvf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "divxf3"
  [(set (match_operand:XF 0 "s_register_operand" "=f,f")
	(div:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G")
		(match_operand:XF 2 "fpu_rhs_operand" "fG,f")))]
  "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
  "@
   dvf%?e\\t%0, %1, %2
   rdf%?e\\t%0, %2, %1"
  [(set_attr "type" "fdivx")
   (set_attr "predicable" "yes")]
)

;; Modulo insns

(define_insn "modsf3"
  [(set (match_operand:SF 0 "s_register_operand" "=f")
	(mod:SF (match_operand:SF 1 "s_register_operand" "f")
		(match_operand:SF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "rmf%?s\\t%0, %1, %2"
  [(set_attr "type" "fdivs")
   (set_attr "predicable" "yes")]
)

(define_insn "moddf3"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mod:DF (match_operand:DF 1 "s_register_operand" "f")
		(match_operand:DF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "rmf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*moddf_esfdf_df"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mod:DF (float_extend:DF
		 (match_operand:SF 1 "s_register_operand" "f"))
		(match_operand:DF 2 "fpu_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "rmf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*moddf_df_esfdf"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mod:DF (match_operand:DF 1 "s_register_operand" "f")
		(float_extend:DF
		 (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT"
  "rmf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*moddf_esfdf_esfdf"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mod:DF (float_extend:DF
		 (match_operand:SF 1 "s_register_operand" "f"))