avr.md

linux下的gcc编译器

   (set_attr "cc" "set_n,clobber,set_n,clobber")])

(define_peephole2
  [(match_scratch:QI 3 "d")
   (set (match_operand:SI 0 "register_operand" "")
	(ashift:SI (match_operand:SI 1 "register_operand" "")
		   (match_operand:QI 2 "const_int_operand" "")))]
  ""
  [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
	      (clobber (match_dup 3))])]
  "if (!avr_peep2_scratch_safe (operands[3]))
     FAIL;")

(define_insn "*ashlsi3_const"
  [(set (match_operand:SI 0 "register_operand"            "=r,r,r")
	(ashift:SI (match_operand:SI 1 "register_operand"  "0,r,0")
		   (match_operand:QI 2 "const_int_operand" "P,O,n")))
   (clobber (match_scratch:QI 3 "=X,X,&d"))]
  "reload_completed"
  "* return ashlsi3_out (insn, operands, NULL);"
  [(set_attr "length" "4,4,10")
   (set_attr "cc" "set_n,clobber,clobber")])

;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; arithmetic shift right

(define_insn "ashrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
		     (match_operand:QI 2 "general_operand" "r,P,K,n,Qm")))]
  ""
  "* return ashrqi3_out (insn, operands, NULL);"
  [(set_attr "length" "5,1,2,5,9")
   (set_attr "cc" "clobber,clobber,clobber,clobber,clobber")])

(define_insn "ashrhi3"
  [(set (match_operand:HI 0 "register_operand"             "=r,r,r,r,r,r")
	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
		     (match_operand:QI 2 "general_operand"  "r,P,O,K,n,Qm")))]
  ""
  "* return ashrhi3_out (insn, operands, NULL);"
  [(set_attr "length" "6,2,4,4,10,10")
   (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "register_operand"             "=r,r,r,r,r,r")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
		     (match_operand:QI 2 "general_operand"  "r,P,O,K,n,Qm")))]
  ""
  "* return ashrsi3_out (insn, operands, NULL);"
  [(set_attr "length" "8,4,6,8,10,12")
   (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])

;; Optimize if a scratch register from LD_REGS happens to be available.

(define_peephole2
  [(match_scratch:QI 3 "d")
   (set (match_operand:HI 0 "register_operand" "")
	(ashiftrt:HI (match_operand:HI 1 "register_operand" "")
		     (match_operand:QI 2 "const_int_operand" "")))]
  ""
  [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
	      (clobber (match_dup 3))])]
  "if (!avr_peep2_scratch_safe (operands[3]))
     FAIL;")

(define_insn "*ashrhi3_const"
  [(set (match_operand:HI 0 "register_operand"              "=r,r,r,r")
	(ashiftrt:HI (match_operand:HI 1 "register_operand"  "0,r,0,0")
		     (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
   (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
  "reload_completed"
  "* return ashrhi3_out (insn, operands, NULL);"
  [(set_attr "length" "2,4,4,10")
   (set_attr "cc" "clobber,set_n,clobber,clobber")])

(define_peephole2
  [(match_scratch:QI 3 "d")
   (set (match_operand:SI 0 "register_operand" "")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
		     (match_operand:QI 2 "const_int_operand" "")))]
  ""
  [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
	      (clobber (match_dup 3))])]
  "if (!avr_peep2_scratch_safe (operands[3]))
     FAIL;")

(define_insn "*ashrsi3_const"
  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
	(ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,r,0")
		     (match_operand:QI 2 "const_int_operand" "P,O,n")))
   (clobber (match_scratch:QI 3 "=X,X,&d"))]
  "reload_completed"
  "* return ashrsi3_out (insn, operands, NULL);"
  [(set_attr "length" "4,4,10")
   (set_attr "cc" "clobber,set_n,clobber")])

;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; logical shift right

(define_insn "lshrqi3"
  [(set (match_operand:QI 0 "register_operand"             "=r,r,r,!d,r,r")
	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
		     (match_operand:QI 2 "general_operand"  "r,P,K,n,n,Qm")))]
  ""
  "* return lshrqi3_out (insn, operands, NULL);"
  [(set_attr "length" "5,1,2,4,6,9")
   (set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])

(define_insn "lshrhi3"
  [(set (match_operand:HI 0 "register_operand"             "=r,r,r,r,r,r")
	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
		     (match_operand:QI 2 "general_operand"  "r,P,O,K,n,Qm")))]
  ""
  "* return lshrhi3_out (insn, operands, NULL);"
  [(set_attr "length" "6,2,2,4,10,10")
   (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand"             "=r,r,r,r,r,r")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
		     (match_operand:QI 2 "general_operand"  "r,P,O,K,n,Qm")))]
  ""
  "* return lshrsi3_out (insn, operands, NULL);"
  [(set_attr "length" "8,4,4,8,10,12")
   (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])

;; Optimize if a scratch register from LD_REGS happens to be available.

(define_peephole2
  [(match_scratch:QI 3 "d")
   (set (match_operand:HI 0 "register_operand" "")
	(lshiftrt:HI (match_operand:HI 1 "register_operand" "")
		     (match_operand:QI 2 "const_int_operand" "")))]
  ""
  [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
	      (clobber (match_dup 3))])]
  "if (!avr_peep2_scratch_safe (operands[3]))
     FAIL;")

(define_insn "*lshrhi3_const"
  [(set (match_operand:HI 0 "register_operand"              "=r,r,r,r")
	(lshiftrt:HI (match_operand:HI 1 "register_operand"  "0,r,0,0")
		     (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
   (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
  "reload_completed"
  "* return lshrhi3_out (insn, operands, NULL);"
  [(set_attr "length" "2,2,4,10")
   (set_attr "cc" "clobber,clobber,clobber,clobber")])

(define_peephole2
  [(match_scratch:QI 3 "d")
   (set (match_operand:SI 0 "register_operand" "")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
		     (match_operand:QI 2 "const_int_operand" "")))]
  ""
  [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
	      (clobber (match_dup 3))])]
  "if (!avr_peep2_scratch_safe (operands[3]))
     FAIL;")

(define_insn "*lshrsi3_const"
  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
	(lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,r,0")
		     (match_operand:QI 2 "const_int_operand" "P,O,n")))
   (clobber (match_scratch:QI 3 "=X,X,&d"))]
  "reload_completed"
  "* return lshrsi3_out (insn, operands, NULL);"
  [(set_attr "length" "4,4,10")
   (set_attr "cc" "clobber,clobber,clobber")])

;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
;; abs

(define_insn "absqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (abs:QI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "sbrc %0,7
	neg %0"
  [(set_attr "length" "2")
   (set_attr "cc" "clobber")])


(define_insn "abssf2"
  [(set (match_operand:SF 0 "register_operand" "=d,r")
        (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
  ""
  "@
	andi %D0,0x7f
	clt\;bld %D0,7"
  [(set_attr "length" "1,2")
   (set_attr "cc" "set_n,clobber")])

;; 0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x
;; neg

(define_insn "negqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (neg:QI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "neg %0"
  [(set_attr "length" "1")
   (set_attr "cc" "set_zn")])

(define_insn "neghi2"
  [(set (match_operand:HI 0 "register_operand"       "=!d,r,&r")
	(neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
  ""
  "@
	com %B0\;neg %A0\;sbci %B0,lo8(-1)
	com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
	clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
  [(set_attr "length" "3,4,4")
   (set_attr "cc" "set_czn,set_n,set_czn")])

(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand"       "=!d,r,&r")
	(neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
  ""
  "@
	com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
	com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
	clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
  [(set_attr_alternative "length"
			 [(const_int 7)
			  (const_int 8)
			  (if_then_else (eq_attr "mcu_enhanced" "yes")
					(const_int 7)
					(const_int 8))])
   (set_attr "cc" "set_czn,set_n,set_czn")])

(define_insn "negsf2"
  [(set (match_operand:SF 0 "register_operand" "=d,r")
	(neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
  ""
  "@
	subi %D0,0x80
	bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
  [(set_attr "length" "1,4")
   (set_attr "cc" "set_n,set_n")])

;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;; not

(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (not:QI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "com %0"
  [(set_attr "length" "1")
   (set_attr "cc" "set_czn")])

(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (not:HI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "com %0
	com %B0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_n")])

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (not:SI (match_operand:SI 1 "register_operand" "0")))]
  ""
  "com %0
	com %B0
	com %C0
	com %D0"
  [(set_attr "length" "4")
   (set_attr "cc" "set_n")])

;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
;; sign extend

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
  ""
  "@
	clr %B0\;sbrc %0,7\;com %B0
	mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
  [(set_attr "length" "3,4")
   (set_attr "cc" "set_n,set_n")])

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
  ""
  "@
	clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
	mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
  [(set_attr "length" "5,6")
   (set_attr "cc" "set_n,set_n")])

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand"               "=r,&r")
        (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
  ""
  "@
	clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
	{mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
  [(set_attr_alternative "length"
			 [(const_int 4)
			  (if_then_else (eq_attr "mcu_enhanced" "yes")
					(const_int 5)
					(const_int 6))])
   (set_attr "cc" "set_n,set_n")])

;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
;; zero extend

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (zero_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
  ""
  "@
	clr %B0
	mov %A0,%A1\;clr %B0"
  [(set_attr "length" "1,2")
   (set_attr "cc" "set_n,set_n")])

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (zero_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
  ""
  "@
	clr %B0\;clr %C0\;clr %D0
	mov %A0,%A1\;clr %B0\;clr %C0\;clr %D0"
  [(set_attr "length" "3,4")
   (set_attr "cc" "set_n,set_n")])

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,&r")
        (zero_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
  ""
  "@
	clr %C0\;clr %D0
	{mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;clr %D0"
  [(set_attr_alternative "length"
			 [(const_int 2)
			  (if_then_else (eq_attr "mcu_enhanced" "yes")
					(const_int 3)
					(const_int 4))])
   (set_attr "cc" "set_n,set_n")])

;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
;; compare

(define_insn "tstqi"
  [(set (cc0)
        (match_operand:QI 0 "register_operand" "r"))]
  ""
  "tst %0"
  [(set_attr "cc" "compare")
   (set_attr "length" "1")])

(define_insn "*negated_tstqi"
  [(set (cc0)
        (neg:QI (match_operand:QI 0 "register_operand" "r")))]
  ""
  "cp __zero_reg__,%0"
  [(set_attr "cc" "compare")
   (set_attr "length" "1")])

(define_insn "tsthi"
  [(set (cc0)
        (match_operand:HI 0 "register_operand" "!w,r"))]
  ""
  "* return out_tsthi (insn,NULL);"
[(set_attr "cc" "compare,compare")
 (set_attr "length" "1,2")])

(define_insn "*negated_tsthi"
  [(set (cc0)
        (neg:HI (match_operand:HI 0 "register_operand" "r")))]
  ""
  "cp __zero_reg__,%A0
	cpc __zero_reg__,%B0"
[(set_attr "cc" "compare")
 (set_attr "length" "2")])

(define_insn "tstsi"
  [(set (cc0)
        (match_operand:SI 0 "register_operand" "r"))]
  ""
  "* return out_tstsi (insn,NULL);"
  [(set_attr "cc" "compare")
   (set_attr "length" "4")])

(define_insn "*negated_tstsi"
  [(set (cc0)
        (neg:SI (match_operand:SI 0 "register_operand" "r")))]
  ""
  "cp __zero_reg__,%A0
	cpc __zero_reg__,%B0
	cpc __zero_reg__,%C0
	cpc __zero_reg__,%D0"
  [(set_attr "cc" "compare")
   (set_attr "length" "4")])


(define_insn "cmpqi"
  [(set (cc0)
        (compare (match_operand:QI 0 "register_operand"  "r,d")
		 (match_operand:QI 1 "nonmemory_operand" "r,i")))]