avr.md

linux下的gcc编译器

	       AS1 (brne,.-8));
     else
       return (AS2 (ld,__tmp_reg__,%a1+) CR_TAB
	       AS2 (st,%a0+,__tmp_reg__)  CR_TAB
	       AS2 (subi,%A2,1) CR_TAB
	       AS2 (sbci,%B2,0) CR_TAB
	       AS1 (brne,.-10));
}"
  [(set_attr "length" "4,5")
   (set_attr "cc" "clobber,clobber")])

;; =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0
;; memset (%0, 0, %1)

(define_expand "clrstrhi"
  [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
		   (const_int 0))
	      (use (match_operand:HI 1 "const_int_operand" ""))
	      (use (match_operand:HI 2 "const_int_operand" "n"))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  "{
  rtx addr0;
  int cnt8;
  enum machine_mode mode;

  if (GET_CODE (operands[1]) != CONST_INT)
    FAIL;

  cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
  mode = cnt8 ? QImode : HImode;
  operands[1] = copy_to_mode_reg (mode,
                                  gen_int_mode (INTVAL (operands[1]), mode));
  operands[3] = operands[1];

  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
  operands[4] = addr0;
  
  operands[0] = gen_rtx (MEM, BLKmode, addr0);
}")

(define_insn "*clrstrqi"
  [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
	(const_int 0))
   (use (match_operand:QI 1 "register_operand" "r"))
   (use (match_operand:QI 2 "const_int_operand" "n"))
   (clobber (match_dup 1))
   (clobber (match_dup 0))]
  ""
  "st %a0+,__zero_reg__
        dec %1
	brne .-6"
  [(set_attr "length" "3")
   (set_attr "cc" "clobber")])

(define_insn "*clrstrhi"
  [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
	(const_int 0))
   (use (match_operand:HI 1 "register_operand" "!w,d"))
   (use (match_operand:HI 2 "const_int_operand" "n,n"))
   (clobber (match_dup 1))
   (clobber (match_dup 0))]
  ""
  "*{
     if (which_alternative==0)
       return (AS2 (st,%a0+,__zero_reg__) CR_TAB
	       AS2 (sbiw,%A1,1) CR_TAB
	       AS1 (brne,.-6));
     else
       return (AS2 (st,%a0+,__zero_reg__) CR_TAB
	       AS2 (subi,%A1,1) CR_TAB
	       AS2 (sbci,%B1,0) CR_TAB
	       AS1 (brne,.-8));
}"
  [(set_attr "length" "3,4")
   (set_attr "cc" "clobber,clobber")])

(define_expand "strlenhi"
    [(set (match_dup 4)
	  (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
		      (match_operand:QI 2 "const_int_operand" "")
		      (match_operand:HI 3 "immediate_operand" "")] 0))
     (set (match_dup 4) (plus:HI (match_dup 4)
				 (const_int -1)))
     (set (match_operand:HI 0 "register_operand" "")
	  (minus:HI (match_dup 4)
		    (match_dup 5)))]
   ""
   "{
  rtx addr;
  if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
    FAIL;
  addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
  operands[1] = gen_rtx (MEM, BLKmode, addr); 
  operands[5] = addr;
  operands[4] = gen_reg_rtx (HImode);
}")

(define_insn "*strlenhi"
  [(set (match_operand:HI 0 "register_operand" "=e")
	(unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
		    (const_int 0)
		    (match_operand:HI 2 "immediate_operand" "i")] 0))]
  ""
  "ld __tmp_reg__,%a0+
	tst __tmp_reg__
	brne .-6"
  [(set_attr "length" "3")
   (set_attr "cc" "clobber")])

;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; add bytes

(define_insn "addqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
        (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
                 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
  ""
  "@
	add %0,%2
	subi %0,lo8(-(%2))
	inc %0
	dec %0"
  [(set_attr "length" "1,1,1,1")
   (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])


(define_expand "addhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(plus:HI (match_operand:HI 1 "register_operand" "")
		 (match_operand:HI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      short tmp = INTVAL (operands[2]);
      operands[2] = GEN_INT(tmp);
    }
}")


(define_insn "*addhi3_zero_extend"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(plus:HI (zero_extend:HI
		  (match_operand:QI 1 "register_operand" "r"))
		 (match_operand:HI 2 "register_operand" "0")))]
  ""
  "add %A0,%1
	adc %B0,__zero_reg__"
  [(set_attr "length" "2")
   (set_attr "cc" "set_n")])

(define_insn "*addhi3_zero_extend1"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(plus:HI (match_operand:HI 1 "register_operand" "%0")
		 (zero_extend:HI
		  (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "add %A0,%2
	adc %B0,__zero_reg__"
  [(set_attr "length" "2")
   (set_attr "cc" "set_n")])

(define_insn "*addhi3_zero_extend2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(plus:HI
	 (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
	 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "add %0,%2
	mov %B0,__zero_reg__
	adc %B0,__zero_reg__"
  [(set_attr "length" "3")
   (set_attr "cc" "set_n")])

(define_insn "*addhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
 	(plus:HI
 	 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
 	 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
  ""
  "@
 	add %A0,%A2\;adc %B0,%B2
 	adiw %A0,%2
 	sbiw %A0,%n2
 	subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
 	sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
 	sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
  [(set_attr "length" "2,1,1,2,3,3")
   (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])

(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
	  (plus:SI
	   (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
	   (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
  ""
  "@
	add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
	adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
	sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
	subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
	sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
	sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
  [(set_attr "length" "4,3,3,4,5,5")
   (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])

(define_insn "*addsi3_zero_extend"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (zero_extend:SI
		  (match_operand:QI 1 "register_operand" "r"))
		 (match_operand:SI 2 "register_operand" "0")))]
  ""
  "add %A0,%1
	adc %B0,__zero_reg__
	adc %C0,__zero_reg__
	adc %D0,__zero_reg__"
  [(set_attr "length" "4")
   (set_attr "cc" "set_n")])

;-----------------------------------------------------------------------------
; sub bytes
(define_insn "subqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,d")
        (minus:QI (match_operand:QI 1 "register_operand" "0,0")
                  (match_operand:QI 2 "nonmemory_operand" "r,i")))]
  ""
  "@
	sub %0,%2
	subi %0,lo8(%2)"
  [(set_attr "length" "1,1")
   (set_attr "cc" "set_czn,set_czn")])

(define_insn "subhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,d")
        (minus:HI (match_operand:HI 1 "register_operand" "0,0")
		  (match_operand:HI 2 "nonmemory_operand" "r,i")))]
  ""
  "@
	sub %A0,%A2\;sbc %B0,%B2
	subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
  [(set_attr "length" "2,2")
   (set_attr "cc" "set_czn,set_czn")])

(define_insn "*subhi3_zero_extend1"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(minus:HI (match_operand:HI 1 "register_operand" "0")
		  (zero_extend:HI
		   (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "sub %A0,%2
	sbc %B0,__zero_reg__"
  [(set_attr "length" "2")
   (set_attr "cc" "set_n")])

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,d")
        (minus:SI (match_operand:SI 1 "register_operand" "0,0")
                 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
  ""
  "@
	sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
	subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
  [(set_attr "length" "4,4")
   (set_attr "cc" "set_czn,set_czn")])

(define_insn "*subsi3_zero_extend"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "0")
		  (zero_extend:SI
		   (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "sub %A0,%2
	sbc %B0,__zero_reg__
	sbc %C0,__zero_reg__
	sbc %D0,__zero_reg__"
  [(set_attr "length" "4")
   (set_attr "cc" "set_n")])

;******************************************************************************
; mul

(define_expand "mulqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(mult:QI (match_operand:QI 1 "register_operand" "")
		 (match_operand:QI 2 "register_operand" "")))]
  ""
  "{
  if (!AVR_ENHANCED)
    {
      emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*mulqi3_enh"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(mult:QI (match_operand:QI 1 "register_operand" "r")
		 (match_operand:QI 2 "register_operand" "r")))]
  "AVR_ENHANCED"
  "mul %1,%2
	mov %0,r0
	clr r1"
  [(set_attr "length" "3")
   (set_attr "cc" "clobber")])

(define_expand "mulqi3_call"
  [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
   (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
   (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
	      (clobber (reg:QI 22))])
   (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
  ""
  "")

(define_insn "*mulqi3_call"
  [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
   (clobber (reg:QI 22))]
  "!AVR_ENHANCED"
  "%~call __mulqi3"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

(define_insn "mulqihi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
		 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
  "AVR_ENHANCED"
  "muls %1,%2
	movw %0,r0
	clr r1"
  [(set_attr "length" "3")
   (set_attr "cc" "clobber")])

(define_insn "umulqihi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
		 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
  "AVR_ENHANCED"
  "mul %1,%2
	movw %0,r0
	clr r1"
  [(set_attr "length" "3")
   (set_attr "cc" "clobber")])

(define_expand "mulhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(mult:HI (match_operand:HI 1 "register_operand" "")
		 (match_operand:HI 2 "register_operand" "")))]
  ""
  "
{
  if (!AVR_ENHANCED)
    {
      emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*mulhi3_enh"
  [(set (match_operand:HI 0 "register_operand" "=&r")
	(mult:HI (match_operand:HI 1 "register_operand" "r")
		 (match_operand:HI 2 "register_operand" "r")))]
  "AVR_ENHANCED"
  "mul %A1,%A2
	movw %0,r0
	mul %A1,%B2
	add %B0,r0
	mul %B1,%A2
	add %B0,r0
	clr r1"
  [(set_attr "length" "7")
   (set_attr "cc" "clobber")])

(define_expand "mulhi3_call"
  [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
   (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
   (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
	      (clobber (reg:HI 22))
	      (clobber (reg:QI 21))])
   (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
  ""
  "")

(define_insn "*mulhi3_call"
  [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
   (clobber (reg:HI 22))
   (clobber (reg:QI 21))]
  "!AVR_ENHANCED"
  "%~call __mulhi3"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
;; All call-used registers clobbered otherwise - normal library call.
(define_expand "mulsi3"
  [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
   (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
   (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
	      (clobber (reg:HI 26))
	      (clobber (reg:HI 30))])
   (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
  "AVR_ENHANCED"
  "")